Channel Trimming Process to Improve Electro-Thermal Characteristics for Sub-3-nm Node Si Nanosheet FETs

IF 2.9 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Electron Devices Pub Date : 2024-10-07 DOI:10.1109/TED.2024.3469171
Sanguk Lee;Jinsu Jeong;Rock-Hyun Baek
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Abstract

This study examined the electrical and thermal behaviors of nanosheet (NS) field-effect transistors (NSFETs) with trimmed channels using a technology computer-aided design (TCAD) simulation. NSFETs are expected to exhibit excellent electrical behaviors owing to thin gate-all-around (GAA) channels. However, NSFETs still suffer from: 1) high punchthrough current ( ${I}_{\text {PTS}}$ ) in the punchthrough stopper (PTS) region and 2) poor heat dissipation by the thin channel thickness. Thus, to resolve these problems, this study proposed NSFETs with trimmed NS channels and a trench gate in the PTS region. This structure can be formed via the deposition of thick silicon layers during Si/SiGe stacking and consequently trimming the silicon regions (NS channels, PTS region) following the channel release. Consequently, the trench gate strengthened the gate controllability for the PTS region, exhibiting remarkable ${I}_{\text {PTS}}$ suppression. In addition, untrimmed thick channel ends improved heat transfer, whereas the trimmed channel centers provided excellent gate controllability. Therefore, the trimming process, which formed trimmed channels and a trench gate, is expected to simultaneously solve the inherent electrical and thermal issues encountered in NSFETs.
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改善 3 纳米以下节点硅纳米片场效应晶体管电热特性的沟道微调工艺
本研究利用技术计算机辅助设计(TCAD)模拟,研究了具有修剪沟道的纳米片(NS)场效应晶体管(NSFET)的电气和热性能。由于采用了薄型全栅极(GAA)沟道,NSFET有望表现出优异的电气性能。然而,NSFET 仍然存在以下问题:1)在穿孔挡板(PTS)区域存在较高的穿孔电流(${I}_{text {PTS}}$);2)由于沟道厚度较薄,散热性能较差。因此,为了解决这些问题,本研究提出了在 PTS 区域具有修剪过的 NS 沟道和沟道栅极的 NSFET。这种结构可以通过在硅/锗堆叠过程中沉积厚硅层,然后在沟道释放后修整硅区域(NS 沟道、PTS 区域)来形成。因此,沟道栅极增强了 PTS 区的栅极可控性,表现出显著的 ${I}_{text {PTS}}$抑制。此外,未修整的厚沟道末端改善了热传导,而修整后的沟道中心则提供了出色的栅极可控性。因此,形成修剪沟道和沟道栅极的修剪工艺有望同时解决 NSFET 中固有的电气和热问题。
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来源期刊
IEEE Transactions on Electron Devices
IEEE Transactions on Electron Devices 工程技术-工程:电子与电气
CiteScore
5.80
自引率
16.10%
发文量
937
审稿时长
3.8 months
期刊介绍: IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors. Tutorial and review papers on these subjects are also published and occasional special issues appear to present a collection of papers which treat particular areas in more depth and breadth.
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