Manipulating Band-to-Band Tunneling Current in Low-Voltage pMOS Devices in BCD Technology: A TCAD and Experimental Investigation

Abstract

This study investigates the issue of reducing band-to-band leakage current in low-voltage (LV) CMOS devices realized using BCD technology. Through TCAD simulations and comprehensive experimental characterization, the influence of key process parameters on leakage current in this category of devices is examined. The presented findings suggest that band-to-band tunneling (B2B) can be significantly mitigated by carefully selecting the rapid thermal processing (RTP) annealing temperature. Subsequently, we address the side effects of the modification of the process parameter on the electrical performance of the devices, aiming to recover affected electrical figures of merit through precise adjustments to the process working point. The study shows that this goal can be reached by a proper modification of the p+ implant energy. In the end, a statistical analysis is presented, with the purpose of understanding the impact of these process changes on the distribution of defects. This research not only proposes a method to tackle the well-known issue of B2B current but also provides valuable insight into the steps required to achieve substantial enhancements in the electrical performance of components by fine-tuning BCD process parameters.