Suppression Effect of Split-Gate Structure on Repetitive Avalanche Stress Induced Degradation for SiC MOSFETs

Abstract

The split-gate (SG) silicon carbide (SiC) MOSFETs with excellent high-frequency (HF) characteristics have been prepared, but studies on their reliability are scarce. The degradation of the electrical parameters and the corresponding mechanisms for the SG SiC MOSFET under repetitive avalanche stress are investigated and compared with those of the planar-gate (PG) SiC MOSFET. The experiments indicate that even though the static characteristics of both types of devices remain unchanged, the degradation in their capacitances varies. Charge injection into the gate oxide above the JFET region remains the dominant degradation mechanism. Degradation is found to be less serious for an SG device. With the help of 3-D TCAD simulations, the electric field distribution under the avalanche breakdown status is simulated. It is found that for the SG SiC MOSFET, the interfacial electric field is less than 1 MV/cm in the polysilicon-etched region. Combined with the smaller polysilicon-covered area in the JFET region, the increment in the capacitance is reduced after enduring the repetitive avalanche stress. Furtherly, the degradations of the gate charge and the switching characteristics are also suppressed.