Placement and routing approach for MQCA-based designs with BFS and A* algorithms

Abstract

Magnetic Quantum-dot Cellular Automata (MQCA) based technologies hold significant promise in outperforming CMOS technology due to their reduced power consumption and increased device density. This new technology has several challenges in carrying tasks like circuit mapping, placement, and routing. This study presents a method for automatically mapping and routing a gate-level circuit using a Nanomagnetic Logic (NML) layout. Our approach leverages the Breadth-First Search algorithm for placement and the A* algorithm for each node’s circuit traversal and route generation. Clock synchronization, layout area, and other essential circuit design elements are skilfully integrated into the proposed algorithms. To validate the effectiveness of the proposed algorithms, we implemented various circuits, including 2:1 & 4:1 multiplexers, 1-bit & 2-bit full adders, XOR gate, and the C17 ISCAS 85 benchmark circuit. Moreover, to demonstrate the scalability of the algorithms, we also present ripple carry adders (RCAs) of different sizes. For a 64-bit RCA, our algorithms achieve significant improvements, with reductions of $\sim$91%–98% in clock zones, $\sim$91%–99% in nanomagnet counts, and a $\sim$99% reduction in the total bounded area compared to the state-of-the-art designs. Furthermore, to ensure the correctness of the proposed algorithms, we provide a detailed simulation analysis of implemented circuits using the NMLSim 2.0 micromagnetic simulator.