Computers & Electrical Engineering最新文献

Optimization of subsampled chrominance and luminance for color image signals 彩色图像信号的下采样色度和亮度优化

IF 4.9 3区计算机科学 Q1 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Computers & Electrical Engineering

Pub Date : 2026-01-17 DOI: 10.1016/j.compeleceng.2026.110943

Ming-An Chung , Ting-Lan Lin , Ding-Yuan Chen , Bang-Hao Liu , Kun-Hu Jiang , Yangming Wen , Mohammad Shahid

The image sensors capture image signals in a color filter array (CFA) format. After demosaicking and RGB-to-YUV conversion, YUV 420 subsampling is performed for image/video compression. In recent work, YUV 420 subsampling is considered in either of two schemes: subsampling the chrominance while keeping the luminance values the same, or finding optimal luminance values given subsampled chrominance values. In this paper, we extended prior work by reducing the search space to a few Y candidates by observing multiple intervals in the pixel distortion curve, and by developing more flexible, structured cost functions to enable further optimization of the recovered pixels. The closed-form solution still requires a parameter set for each pixel location. Therefore, several methods for reducing complexity are proposed. In comparison to previous methods evaluated on two benchmark datasets, IMAX and SCI, our approach consistently improves image quality (measured in dB) while incurring only minimal increases in computation time (in seconds). Specifically, for the SCI dataset, relative to the Unoptimized Luminance method, we achieve an average CPSNR increase of 3.69 to 7.15 dB, accompanied by an increase in computation time of 12.35 to 13.63 s. In contrast, the Optimized Luminance method yields an average CPSNR improvement of 2.84 to 5.67 dB, with a lower computation time of 0.24 to 3.94 s. For the IMAX dataset, when compared to the unoptimized Luminance method, we note an average CPSNR enhancement of 1.66 to 4.58 dB, with a corresponding rise in computation time of 7.00 to 8.71 s. Meanwhile, the Optimized Luminance method results in an average CPSNR increase of 0.4 to 3.73 dB, with a modest computation time increase of 2.07 to 2.86 s.

图像传感器以彩色滤波阵列（CFA）格式捕获图像信号。在去马赛克和rgb -YUV转换后，YUV 420子采样进行图像/视频压缩。在最近的工作中，yuv420的子采样有两种方案：一种是在保持亮度值不变的情况下对亮度进行子采样，另一种是在给定子采样的亮度值的情况下找到最优亮度值。在本文中，我们扩展了之前的工作，通过观察像素失真曲线中的多个间隔，将搜索空间减少到几个Y候选者，并通过开发更灵活的结构化成本函数来进一步优化恢复的像素。封闭形式的解决方案仍然需要为每个像素位置设置参数。因此，提出了几种降低复杂性的方法。与之前在两个基准数据集（IMAX和SCI）上评估的方法相比，我们的方法持续提高了图像质量（以dB为单位），同时只增加了很小的计算时间（以秒为单位）。具体而言，对于SCI数据集，相对于Unoptimized Luminance方法，我们实现了平均CPSNR增加3.69至7.15 dB，同时计算时间增加12.35至13.63 s。相比之下，优化亮度方法的平均CPSNR提高了2.84 ~ 5.67 dB，计算时间较低，为0.24 ~ 3.94 s。对于IMAX数据集，与未优化的亮度方法相比，我们注意到平均CPSNR提高了1.66至4.58 dB，计算时间相应增加了7.00至8.71 s。同时，优化亮度方法的CPSNR平均提高了0.4 ~ 3.73 dB，计算时间增加了2.07 ~ 2.86 s。

{"title":"Optimization of subsampled chrominance and luminance for color image signals","authors":"Ming-An Chung , Ting-Lan Lin , Ding-Yuan Chen , Bang-Hao Liu , Kun-Hu Jiang , Yangming Wen , Mohammad Shahid","doi":"10.1016/j.compeleceng.2026.110943","DOIUrl":"10.1016/j.compeleceng.2026.110943","url":null,"abstract":"<div><div>The image sensors capture image signals in a color filter array (CFA) format. After demosaicking and RGB-to-YUV conversion, YUV 420 subsampling is performed for image/video compression. In recent work, YUV 420 subsampling is considered in either of two schemes: subsampling the chrominance while keeping the luminance values the same, or finding optimal luminance values given subsampled chrominance values. In this paper, we extended prior work by reducing the search space to a few Y candidates by observing multiple intervals in the pixel distortion curve, and by developing more flexible, structured cost functions to enable further optimization of the recovered pixels. The closed-form solution still requires a parameter set for each pixel location. Therefore, several methods for reducing complexity are proposed. In comparison to previous methods evaluated on two benchmark datasets, IMAX and SCI, our approach consistently improves image quality (measured in dB) while incurring only minimal increases in computation time (in seconds). Specifically, for the SCI dataset, relative to the Unoptimized Luminance method, we achieve an average CPSNR increase of 3.69 to 7.15 dB, accompanied by an increase in computation time of 12.35 to 13.63 s. In contrast, the Optimized Luminance method yields an average CPSNR improvement of 2.84 to 5.67 dB, with a lower computation time of 0.24 to 3.94 s. For the IMAX dataset, when compared to the unoptimized Luminance method, we note an average CPSNR enhancement of 1.66 to 4.58 dB, with a corresponding rise in computation time of 7.00 to 8.71 s. Meanwhile, the Optimized Luminance method results in an average CPSNR increase of 0.4 to 3.73 dB, with a modest computation time increase of 2.07 to 2.86 s.</div></div>","PeriodicalId":50630,"journal":{"name":"Computers & Electrical Engineering","volume":"131 ","pages":"Article 110943"},"PeriodicalIF":4.9,"publicationDate":"2026-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145978230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A hybrid fuzzy logic-based energy management strategy for grid-connected photovoltaic microgrids with energy storage optimization 基于混合模糊逻辑的储能优化并网光伏微电网能量管理策略

IF 4.9 3区计算机科学 Q1 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Computers & Electrical Engineering

Pub Date : 2026-01-17 DOI: 10.1016/j.compeleceng.2026.110977

Renjin , Liyunhe , Gongshenggao , Biantao

A microgrid is an advanced infrastructure that offers increased sustainability, dependability, and local energy autonomy by incorporating renewable and hybrid energy sources into the utility system. However, uncertainties arising from the intermittent nature of renewable sources, fluctuating loads, and dynamic electricity market prices present significant challenges for efficient operation. Traditional heuristic-based energy management systems (EMS) rely on forecasted data but often lack precision and adaptability under real-world variability. To address these limitations, this research proposes a novel Fuzzy Logic Controller-based EMS (FLC-EMS) for optimizing microgrid performance. Unlike rigid rule-based or computationally intensive linear programming (LP) methods, the proposed FLC-EMS combines intelligent decision-making with responsiveness and cost-effectiveness. Simulation results demonstrate that the FLC-EMS outperforms both heuristic and LP-based EMS strategies. Specifically, it achieves cost savings of approximately 8.1% on clear days and 16.6% on cloudy days compared to heuristic methods, while offering additional savings of 1.6–5.5% over LP-based optimization. Furthermore, FLC-EMS reduces grid energy usage and effectively manages state-of-charge (SoC) variations, resulting in enhanced utilization of renewable resources and lower reliance on grid power. The integrated microgrid model and EMS framework developed in this study serve as a robust platform for smart grid applications, offering scalability, real-time adaptability, and improved consumer economics. This work positions the FLC-EMS as a promising candidate for advanced microgrid control, paving the way for resilient and intelligent next-generation power systems.

微电网是一种先进的基础设施，通过将可再生能源和混合能源纳入公用事业系统，提高了可持续性、可靠性和地方能源自主权。然而，可再生能源的间歇性、负荷波动和电力市场价格动态所带来的不确定性，对高效运行构成了重大挑战。传统的启发式能源管理系统（EMS）依赖于预测数据，但在实际变化情况下往往缺乏精度和适应性。为了解决这些限制，本研究提出了一种新的基于模糊逻辑控制器的EMS （FLC-EMS）来优化微电网性能。与严格的基于规则或计算密集型线性规划（LP）方法不同，FLC-EMS将智能决策与响应性和成本效益相结合。仿真结果表明，FLC-EMS优于启发式和基于lp的EMS策略。具体来说，与启发式方法相比，它在晴天节省了大约8.1%的成本，在阴天节省了16.6%的成本，同时比基于lp的优化节省了1.6-5.5%的成本。此外，FLC-EMS减少了电网能源的使用，有效地管理了荷电状态（SoC）的变化，从而提高了可再生资源的利用率，降低了对电网的依赖。本研究开发的集成微电网模型和EMS框架可作为智能电网应用的强大平台，提供可扩展性、实时适应性和改进的消费者经济。这项工作将FLC-EMS定位为先进微电网控制的有前途的候选者，为弹性和智能的下一代电力系统铺平了道路。

{"title":"A hybrid fuzzy logic-based energy management strategy for grid-connected photovoltaic microgrids with energy storage optimization","authors":"Renjin , Liyunhe , Gongshenggao , Biantao","doi":"10.1016/j.compeleceng.2026.110977","DOIUrl":"10.1016/j.compeleceng.2026.110977","url":null,"abstract":"<div><div>A microgrid is an advanced infrastructure that offers increased sustainability, dependability, and local energy autonomy by incorporating renewable and hybrid energy sources into the utility system. However, uncertainties arising from the intermittent nature of renewable sources, fluctuating loads, and dynamic electricity market prices present significant challenges for efficient operation. Traditional heuristic-based energy management systems (EMS) rely on forecasted data but often lack precision and adaptability under real-world variability. To address these limitations, this research proposes a novel Fuzzy Logic Controller-based EMS (FLC-EMS) for optimizing microgrid performance. Unlike rigid rule-based or computationally intensive linear programming (LP) methods, the proposed FLC-EMS combines intelligent decision-making with responsiveness and cost-effectiveness. Simulation results demonstrate that the FLC-EMS outperforms both heuristic and LP-based EMS strategies. Specifically, it achieves cost savings of approximately 8.1% on clear days and 16.6% on cloudy days compared to heuristic methods, while offering additional savings of 1.6–5.5% over LP-based optimization. Furthermore, FLC-EMS reduces grid energy usage and effectively manages state-of-charge (SoC) variations, resulting in enhanced utilization of renewable resources and lower reliance on grid power. The integrated microgrid model and EMS framework developed in this study serve as a robust platform for smart grid applications, offering scalability, real-time adaptability, and improved consumer economics. This work positions the FLC-EMS as a promising candidate for advanced microgrid control, paving the way for resilient and intelligent next-generation power systems.</div></div>","PeriodicalId":50630,"journal":{"name":"Computers & Electrical Engineering","volume":"131 ","pages":"Article 110977"},"PeriodicalIF":4.9,"publicationDate":"2026-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145978231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hybrid tree-based indexing for efficient data retrieval in Smart Grids 基于混合树的智能电网数据检索方法

IF 4.9 3区计算机科学 Q1 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Computers & Electrical Engineering

Pub Date : 2026-01-17 DOI: 10.1016/j.compeleceng.2026.110973

Abdelbacet Brahmia , Zineddine Kouahla , Ala Eddine Benrazek , Brahim Farou , Hamid Seridi

The Smart Grid, a prominent IoT application, is experiencing rapid growth driven by the proliferation of connected embedded devices. This evolution has resulted in an exponential increase in time-series data, emphasizing the need for efficient data storage and retrieval mechanisms, particularly for real-time IoT environments. Existing indexing structures primarily focus on either time-based or consumption-based organization, often overlooking the interdependence between these dimensions, which limits their query efficiency. To address this limitation, this paper introduces a novel Temporal-Consumption Binary Tree (TCB-Tree), a hybrid tree-based indexing structure that jointly exploits temporal and consumption attributes for efficient data retrieval. The proposed method operates in three main phases: (i) horizontal segmentation, which applies clustering to identify key consumption levels; (ii) vertical segmentation, which groups temporally successive data within the same consumption range; and (iii) hybrid index construction, where internal nodes index time while leaf nodes index consumption patterns. Experimental evaluation using three real-world datasets demonstrates that the TCB-Tree achieves rapid construction times (under 0.20 s) and efficient hybrid query execution (under 0.9 s) on large datasets, while maintaining minimal storage overhead (below 18%). These results confirm the scalability, efficiency, and suitability of the proposed structure for Smart Grid and real-time IoT applications.

智能电网是一个突出的物联网应用，在连接嵌入式设备激增的推动下，正在经历快速增长。这种演变导致时间序列数据呈指数级增长，强调了对高效数据存储和检索机制的需求，特别是对于实时物联网环境。现有的索引结构主要关注基于时间或基于消费的组织，通常忽略了这些维度之间的相互依赖关系，从而限制了它们的查询效率。为了解决这一限制，本文引入了一种新的时间消费二叉树（TCB-Tree），这是一种混合的基于树的索引结构，它联合利用时间和消费属性来进行有效的数据检索。该方法分为三个主要阶段：(i)水平分割，利用聚类来识别关键消费水平；（ii）垂直分割，将同一消费范围内的时间连续数据分组；(3)混合索引构建，其中内部节点索引时间，叶节点索引消费模式。使用三个真实数据集的实验评估表明，TCB-Tree在大型数据集上实现了快速的构建时间（低于0.20 s）和高效的混合查询执行（低于0.9 s），同时保持最小的存储开销（低于18%）。这些结果证实了所提出的结构在智能电网和实时物联网应用中的可扩展性、效率和适用性。

{"title":"Hybrid tree-based indexing for efficient data retrieval in Smart Grids","authors":"Abdelbacet Brahmia , Zineddine Kouahla , Ala Eddine Benrazek , Brahim Farou , Hamid Seridi","doi":"10.1016/j.compeleceng.2026.110973","DOIUrl":"10.1016/j.compeleceng.2026.110973","url":null,"abstract":"<div><div>The Smart Grid, a prominent IoT application, is experiencing rapid growth driven by the proliferation of connected embedded devices. This evolution has resulted in an exponential increase in time-series data, emphasizing the need for efficient data storage and retrieval mechanisms, particularly for real-time IoT environments. Existing indexing structures primarily focus on either time-based or consumption-based organization, often overlooking the interdependence between these dimensions, which limits their query efficiency. To address this limitation, this paper introduces a novel Temporal-Consumption Binary Tree (TCB-Tree), a hybrid tree-based indexing structure that jointly exploits temporal and consumption attributes for efficient data retrieval. The proposed method operates in three main phases: (i) horizontal segmentation, which applies clustering to identify key consumption levels; (ii) vertical segmentation, which groups temporally successive data within the same consumption range; and (iii) hybrid index construction, where internal nodes index time while leaf nodes index consumption patterns. Experimental evaluation using three real-world datasets demonstrates that the TCB-Tree achieves rapid construction times (under 0.20 s) and efficient hybrid query execution (under 0.9 s) on large datasets, while maintaining minimal storage overhead (below 18%). These results confirm the scalability, efficiency, and suitability of the proposed structure for Smart Grid and real-time IoT applications.</div></div>","PeriodicalId":50630,"journal":{"name":"Computers & Electrical Engineering","volume":"131 ","pages":"Article 110973"},"PeriodicalIF":4.9,"publicationDate":"2026-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145978233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A high-efficiency three-phase CMOS RF–DC rectifier for low-power IoT applications 一种用于低功耗物联网应用的高效三相CMOS RF-DC整流器

IF 4.9 3区计算机科学 Q1 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Computers & Electrical Engineering

Pub Date : 2026-01-17 DOI: 10.1016/j.compeleceng.2026.110946

Ahmed Reda Mohamed , Abdulaziz Al-Khulaifi , Muneer A. Al Absi

This paper presents a high-efficiency complementary metal–oxide–semiconductor (CMOS) radio-frequency energy harvesting rectifier based on a novel three-phase architecture for self-powered Internet of Things nodes and implantable biomedical devices. The proposed architecture routes the received radio-frequency signal into three equal-amplitude paths with phase shifts of 0°, 120°, and 240°. It enables time-interleaved parallel rectification thereby improving power conversion efficiency (PCE) and output voltage stability. Implemented in a 180 nm CMOS technology, the rectifier occupies a compact silicon area of

47.88 μ m \times 88.8 μ m

and operates at 920 MHz. Simulation results demonstrate a peak PCE of 81% at an input power of

- 25.8

dBm, a dynamic range of 21 dB, and a sensitivity of

- 10.5

dBm, delivering a regulated 1 V output across a 100 k

Ω

load. The effects of practical parasitic components, including bond wires, pads, and printed circuit board traces, are incorporated into the design of the input matching network, resulting in a reflection coefficient of approximately

- 20

dB at the operating frequency. Furthermore, statistical Monte Carlo and process–voltage–temperature analyses are performed to assess post-fabrication robustness. Compared with conventional single-phase rectifiers, the proposed three-phase architecture achieves higher efficiency and lower output voltage ripple for low-power energy-harvesting applications.

本文提出了一种基于新型三相结构的高效互补金属氧化物半导体（CMOS）射频能量收集整流器，用于自供电的物联网节点和植入式生物医学设备。所提出的架构将接收到的射频信号路由到三个相移为0°，120°和240°的等幅路径中。它可以实现时间交错并联整流，从而提高功率转换效率（PCE）和输出电压稳定性。该整流器采用180nm CMOS技术，占地面积为47.88μm×88.8μm，工作频率为920mhz。仿真结果表明，在输入功率为- 25.8 dBm时，峰值PCE为81%，动态范围为21 dB，灵敏度为- 10.5 dBm，在100 kΩ负载下提供稳压1v输出。实际寄生元件的影响，包括键合线、焊盘和印刷电路板走线，被纳入输入匹配网络的设计中，导致在工作频率下的反射系数约为- 20 dB。此外，统计蒙特卡罗和过程电压-温度分析进行了评估后制造稳健性。与传统的单相整流器相比，所提出的三相结构在低功耗能量收集应用中具有更高的效率和更低的输出电压纹波。

{"title":"A high-efficiency three-phase CMOS RF–DC rectifier for low-power IoT applications","authors":"Ahmed Reda Mohamed , Abdulaziz Al-Khulaifi , Muneer A. Al Absi","doi":"10.1016/j.compeleceng.2026.110946","DOIUrl":"10.1016/j.compeleceng.2026.110946","url":null,"abstract":"<div><div>This paper presents a high-efficiency complementary metal–oxide–semiconductor (CMOS) radio-frequency energy harvesting rectifier based on a novel three-phase architecture for self-powered Internet of Things nodes and implantable biomedical devices. The proposed architecture routes the received radio-frequency signal into three equal-amplitude paths with phase shifts of 0°, 120°, and 240°. It enables time-interleaved parallel rectification thereby improving power conversion efficiency (PCE) and output voltage stability. Implemented in a 180 nm CMOS technology, the rectifier occupies a compact silicon area of <span><math><mrow><mn>47</mn><mo>.</mo><mn>88</mn><mspace></mspace><mi>μ</mi><mtext>m</mtext><mo>×</mo><mn>88</mn><mo>.</mo><mn>8</mn><mspace></mspace><mi>μ</mi><mtext>m</mtext></mrow></math></span> and operates at 920 MHz. Simulation results demonstrate a peak PCE of 81% at an input power of <span><math><mrow><mo>−</mo><mn>25</mn><mo>.</mo><mn>8</mn></mrow></math></span> dBm, a dynamic range of 21 dB, and a sensitivity of <span><math><mrow><mo>−</mo><mn>10</mn><mo>.</mo><mn>5</mn></mrow></math></span> dBm, delivering a regulated 1 V output across a 100 k<span><math><mi>Ω</mi></math></span> load. The effects of practical parasitic components, including bond wires, pads, and printed circuit board traces, are incorporated into the design of the input matching network, resulting in a reflection coefficient of approximately <span><math><mrow><mo>−</mo><mn>20</mn></mrow></math></span> dB at the operating frequency. Furthermore, statistical Monte Carlo and process–voltage–temperature analyses are performed to assess post-fabrication robustness. Compared with conventional single-phase rectifiers, the proposed three-phase architecture achieves higher efficiency and lower output voltage ripple for low-power energy-harvesting applications.</div></div>","PeriodicalId":50630,"journal":{"name":"Computers & Electrical Engineering","volume":"131 ","pages":"Article 110946"},"PeriodicalIF":4.9,"publicationDate":"2026-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145978317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of lightweight image encryption scheme for saliency protection in autonomous control systems 自主控制系统中图像显著性保护的轻量级加密方案设计

IF 4.9 3区计算机科学 Q1 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Computers & Electrical Engineering

Pub Date : 2026-01-17 DOI: 10.1016/j.compeleceng.2026.110966

Lal Said , Muhammad Amin

Autonomous and remotely operated systems rely on image data for critical decision-making, yet these images are often sent over insecure channels, making them vulnerable to interception or tampering. This paper presents a lightweight image encryption scheme that uses Substitution–Permutation Network architecture with modular arithmetic-based block permutation and dynamically generated chaos-driven substitution boxes. The scheme employs dual key-dependent substitution and exclusive OR operations, ensuring that even a single-bit key change produce a completely different encrypted output. Security analysis shows a large key space, strong resistance to brute force attacks, high entropy, and desirable statistical properties. The proposed method achieves higher throughput than conventional ciphers while preserving salient image content even under pixel loss. These results demonstrate that the scheme provides secure and efficient image protection for resource-constrained environments.

自主和远程操作系统依赖图像数据进行关键决策，然而这些图像通常通过不安全的通道发送，使其容易被拦截或篡改。本文提出了一种轻量级的图像加密方案，该方案采用基于模块化算法的块置换和动态生成的混沌驱动替换盒的替换置换网络体系结构。该方案采用双密钥依赖替换和排他或操作，确保即使是单个密钥更改也会产生完全不同的加密输出。安全性分析显示密钥空间大、抗暴力攻击能力强、高熵和理想的统计特性。该方法比传统密码实现了更高的吞吐量，即使在像素丢失的情况下也能保持显著的图像内容。结果表明，该方案为资源受限环境提供了安全有效的图像保护。

引用次数: 0

A novel hybrid cheetah dung beetle optimization algorithm to solve cloud-fog scheduling problems 一种新的混合猎豹屎壳郎优化算法求解云雾调度问题

IF 4.9 3区计算机科学 Q1 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Computers & Electrical Engineering

Pub Date : 2026-01-17 DOI: 10.1016/j.compeleceng.2026.110968

Rakesh Reddy Gurrala, Sampath Kumar Tallapally

The Internet of Things (IoT) revolution has resulted in massive data generation, requiring effective processing. Due to their proximity, tasks that demand a prompt response are sent to the fog node. In contrast, complex tasks are transferred to the cloud due to its massive processing capacity. Transferring tasks to the fog reduces the transmission latency while increasing energy consumption. In contrast, moving work to the cloud lowers energy consumption but increases transmission latency owing to long distances. Therefore, to balance the trade-offs between energy consumption and transmission delay, a hybrid Cheetah Dung Beetle Optimization Algorithm (CDBOA) based job scheduling strategy is used in this work. This hybrid algorithm balances local exploitation and global exploration by integrating the dung beetle optimization algorithm (DBOA) with the cheetah optimization algorithm (COA). This methodology effectively assigns jobs to fog and cloud resources according to their processing requirements and delay sensitivity, guaranteeing effective processing and energy conservation. The effectiveness of the proposed method has been evaluated using NASA iPSC and HPC2N workloads. The results show that the recommended approach performs better than other methods, with 12.64%, 27.60%, 21.55%, and 10.16% improvements for makespan, energy consumption, cost and delay, demonstrating the robustness of the suggested method.

物联网（IoT）革命导致了大量数据的产生，需要有效的处理。由于它们的接近性，需要快速响应的任务被发送到雾节点。相比之下，复杂的任务由于其庞大的处理能力而转移到云上。将任务转移到雾中减少了传输延迟，同时增加了能量消耗。相比之下，将工作转移到云端可以降低能耗，但由于距离较远，会增加传输延迟。因此，为了平衡能量消耗和传输延迟之间的平衡，本文采用了一种基于混合猎豹屎壳虫优化算法（CDBOA）的作业调度策略。该算法将屎壳虫优化算法（DBOA）与猎豹优化算法（COA）相结合，平衡了局部开发与全局探索。该方法根据雾和云资源的处理需求和延迟敏感性，有效地为雾和云资源分配任务，保证了有效的处理和节能。采用NASA iPSC和HPC2N工作负载对所提出方法的有效性进行了评估。结果表明，该方法在完工时间、能耗、成本和延迟方面的性能分别提高了12.64%、27.60%、21.55%和10.16%，证明了该方法的鲁棒性。

{"title":"A novel hybrid cheetah dung beetle optimization algorithm to solve cloud-fog scheduling problems","authors":"Rakesh Reddy Gurrala, Sampath Kumar Tallapally","doi":"10.1016/j.compeleceng.2026.110968","DOIUrl":"10.1016/j.compeleceng.2026.110968","url":null,"abstract":"<div><div>The Internet of Things (IoT) revolution has resulted in massive data generation, requiring effective processing. Due to their proximity, tasks that demand a prompt response are sent to the fog node. In contrast, complex tasks are transferred to the cloud due to its massive processing capacity. Transferring tasks to the fog reduces the transmission latency while increasing energy consumption. In contrast, moving work to the cloud lowers energy consumption but increases transmission latency owing to long distances. Therefore, to balance the trade-offs between energy consumption and transmission delay, a hybrid Cheetah Dung Beetle Optimization Algorithm (CDBOA) based job scheduling strategy is used in this work. This hybrid algorithm balances local exploitation and global exploration by integrating the dung beetle optimization algorithm (DBOA) with the cheetah optimization algorithm (COA). This methodology effectively assigns jobs to fog and cloud resources according to their processing requirements and delay sensitivity, guaranteeing effective processing and energy conservation. The effectiveness of the proposed method has been evaluated using NASA iPSC and HPC2N workloads. The results show that the recommended approach performs better than other methods, with 12.64%, 27.60%, 21.55%, and 10.16% improvements for makespan, energy consumption, cost and delay, demonstrating the robustness of the suggested method.</div></div>","PeriodicalId":50630,"journal":{"name":"Computers & Electrical Engineering","volume":"131 ","pages":"Article 110968"},"PeriodicalIF":4.9,"publicationDate":"2026-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145978232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hierarchical mobile-dense convolutional architecture for tampered image detection using focal optimization with quantized edge TPU deployment 采用量化边缘TPU部署的焦点优化的分层移动密集卷积结构篡改图像检测

IF 4.9 3区计算机科学 Q1 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Computers & Electrical Engineering

Pub Date : 2026-01-16 DOI: 10.1016/j.compeleceng.2026.110979

Badam Shanmukha Venkata Vinayak , Rama Muni Reddy Yanamala , Rayappa David Amar Raj , Archana Pallakonda

The availability of powerful digital editing tools has made image tampering increasingly sophisticated, posing significant challenges to journalism, forensics, and social media authenticity. To address the limitations of conventional and transformer-based forgery detection approaches – which often suffer from feature redundancy, compressibility instability, and high computational demands – this study introduces a deep learning architecture for tampered image detection. The model integrates a MobileNetV2-based encoder for compact spatial feature extraction, multi-scale hierarchical feature reuse blocks inspired by DenseNet, and a U-Net-type decoder for precise forgery localization. Class imbalance is mitigated using an enhanced binary classifier with focal loss. The entire model is quantized and deployed on a Google Coral Edge TPU, achieving real-time classification performance (approximately 135 ms per image) in low-power, resource-limited environments. The model is trained and tested on four benchmark forgery datasets – CASIA v1, Columbia, MICC-F2000, and Defacto-Splicing – and demonstrates excellent results: AUC = 1.00 and accuracy = 99% on Defacto, AUC = 0.967 and F1-score = 0.915 on Columbia, and strong performance on both high-resolution (MICC-F2000) and compressed (CASIA v1) datasets. Comparative analyses show that the proposed approach outperforms recent CNN- and Transformer-based methods while using only 5.7 million parameters, confirming its efficacy, scalability, and suitability for embedded AI systems. Thus, the proposed method represents a lightweight, hardware-deployable, and interpretable solution for robust image forgery detection.

强大的数字编辑工具的可用性使得图像篡改变得越来越复杂，对新闻业、法医学和社交媒体的真实性构成了重大挑战。为了解决传统的和基于变压器的伪造检测方法的局限性——通常存在特征冗余、可压缩性不稳定和高计算需求——本研究引入了一种用于篡改图像检测的深度学习架构。该模型集成了基于mobilenetv2的编码器，用于紧凑的空间特征提取，受DenseNet启发的多尺度分层特征重用块，以及u - net类型的解码器，用于精确的伪造定位。类失衡是减轻使用增强的二元分类器与焦点损失。整个模型被量化并部署在谷歌Coral Edge TPU上，在低功耗、资源有限的环境中实现实时分类性能（每张图像约135毫秒）。该模型在四个基准伪造数据集（CASIA v1、Columbia、mic - f2000和Defacto- splicing）上进行了训练和测试，并展示了出色的结果：Defacto上的AUC = 1.00，准确率= 99%，Columbia上的AUC = 0.967, F1-score = 0.915，在高分辨率（mic - f2000）和压缩（CASIA v1）数据集上都表现出色。对比分析表明，所提出的方法在仅使用570万个参数的情况下优于最近基于CNN和transformer的方法，证实了其有效性、可扩展性和对嵌入式人工智能系统的适用性。因此，所提出的方法代表了一种轻量级、硬件可部署和可解释的鲁棒图像伪造检测解决方案。

{"title":"Hierarchical mobile-dense convolutional architecture for tampered image detection using focal optimization with quantized edge TPU deployment","authors":"Badam Shanmukha Venkata Vinayak , Rama Muni Reddy Yanamala , Rayappa David Amar Raj , Archana Pallakonda","doi":"10.1016/j.compeleceng.2026.110979","DOIUrl":"10.1016/j.compeleceng.2026.110979","url":null,"abstract":"<div><div>The availability of powerful digital editing tools has made image tampering increasingly sophisticated, posing significant challenges to journalism, forensics, and social media authenticity. To address the limitations of conventional and transformer-based forgery detection approaches – which often suffer from feature redundancy, compressibility instability, and high computational demands – this study introduces a deep learning architecture for tampered image detection. The model integrates a MobileNetV2-based encoder for compact spatial feature extraction, multi-scale hierarchical feature reuse blocks inspired by DenseNet, and a U-Net-type decoder for precise forgery localization. Class imbalance is mitigated using an enhanced binary classifier with focal loss. The entire model is quantized and deployed on a Google Coral Edge TPU, achieving real-time classification performance (approximately 135 ms per image) in low-power, resource-limited environments. The model is trained and tested on four benchmark forgery datasets – CASIA v1, Columbia, MICC-F2000, and Defacto-Splicing – and demonstrates excellent results: AUC = 1.00 and accuracy = 99% on Defacto, AUC = 0.967 and F1-score = 0.915 on Columbia, and strong performance on both high-resolution (MICC-F2000) and compressed (CASIA v1) datasets. Comparative analyses show that the proposed approach outperforms recent CNN- and Transformer-based methods while using only 5.7 million parameters, confirming its efficacy, scalability, and suitability for embedded AI systems. Thus, the proposed method represents a lightweight, hardware-deployable, and interpretable solution for robust image forgery detection.</div></div>","PeriodicalId":50630,"journal":{"name":"Computers & Electrical Engineering","volume":"131 ","pages":"Article 110979"},"PeriodicalIF":4.9,"publicationDate":"2026-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145978307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimized 2-D FIR filter bank architecture using various symmetries with parallel processing and DA 利用并行处理和数据处理优化了二维FIR滤波器组结构

IF 4.9 3区计算机科学 Q1 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Computers & Electrical Engineering

Pub Date : 2026-01-16 DOI: 10.1016/j.compeleceng.2026.110941

Venkata Krishna Odugu , P. Ramakrishna , T. Vasudeva Reddy , G Harish Babu , Janardhanarao S

In this study, a new Filter Bank (FB) architecture for a 2-D FIR filter and implementation in VLSI design with the help of symmetric processing, parallelism, and Distributed Arithmetic (DA) ideas are presented. This work is motivated by the need for hardware-efficient 2D FIR filter architectures that reduce computational complexity, Power Consumption (PC), and resource usage in real-time image processing applications. Parallel processing is incorporated into the design to boost throughput and to decrease the quantity of multipliers, symmetry is introduced into the coefficients of the filter. In place of the remaining multipliers, Dual Port-Look-Up Table (DP-LUT)-based DA are proposed to reduce the area and power. Four types of symmetries are considered, and each architecture is explored and implemented using the proposed DA approach. Finally, all these filter structures are integrated by considering a common memory module and a control logic. Memory reuse and sharing are made possible by the FB design, which also allows for parallel processing. The suggested FB design has low resource requirements in terms of both memory and processing power. The hardware utilization synthesis summary is assessed for the target device of the Field Programmable Gate Array (FPGA). After that, the design is synthesized in 45 nm CMOS technology using Cadence's Genus tools for ASIC design. Existing 2-D FIR filter designs and traditional multiplier-based filter architectures are analyzed in terms of area, latency, and PC reports. The proposed FB architecture achieves up to 98.04% reduction in ADP and up to 64.51% reduction in PDP compared to existing designs, highlighting its efficiency in both area and power optimization. The proposed work's layout is then provided, including the Innovus tools used to determine the place and route.

在本研究中，提出了一种新的用于二维FIR滤波器的滤波器组（FB）架构，并利用对称处理、并行性和分布式算法（DA）思想在VLSI设计中实现。这项工作的动机是需要硬件高效的2D FIR滤波器架构，以降低实时图像处理应用中的计算复杂性、功耗（PC）和资源使用。为了提高吞吐量和减少乘法器的数量，设计中引入了并行处理，并在滤波器系数中引入了对称性。采用双端口查找表（Dual port - lookup Table, DP-LUT）代替剩余的乘法器来减少面积和功耗。考虑了四种类型的对称性，并使用所提出的数据处理方法探索和实现了每种体系结构。最后，通过考虑公共存储模块和控制逻辑，将所有这些滤波器结构集成在一起。FB设计使得内存重用和共享成为可能，它还允许并行处理。建议的FB设计在内存和处理能力方面具有较低的资源需求。对现场可编程门阵列（FPGA）目标器件的硬件利用率进行了综合评价。之后，使用Cadence的Genus工具进行ASIC设计，在45 nm CMOS技术中进行设计合成。从面积、延迟和PC报告等方面分析了现有的二维FIR滤波器设计和传统的基于乘法器的滤波器架构。与现有设计相比，所提出的FB架构实现了高达98.04%的ADP降低和高达64.51%的PDP降低，突出了其在面积和功耗优化方面的效率。然后提供建议的工作布局，包括用于确定地点和路线的Innovus工具。

{"title":"Optimized 2-D FIR filter bank architecture using various symmetries with parallel processing and DA","authors":"Venkata Krishna Odugu , P. Ramakrishna , T. Vasudeva Reddy , G Harish Babu , Janardhanarao S","doi":"10.1016/j.compeleceng.2026.110941","DOIUrl":"10.1016/j.compeleceng.2026.110941","url":null,"abstract":"<div><div>In this study, a new Filter Bank (FB) architecture for a 2-D FIR filter and implementation in VLSI design with the help of symmetric processing, parallelism, and Distributed Arithmetic (DA) ideas are presented. This work is motivated by the need for hardware-efficient 2D FIR filter architectures that reduce computational complexity, Power Consumption (PC), and resource usage in real-time image processing applications. Parallel processing is incorporated into the design to boost throughput and to decrease the quantity of multipliers, symmetry is introduced into the coefficients of the filter. In place of the remaining multipliers, Dual Port-Look-Up Table (DP-LUT)-based DA are proposed to reduce the area and power. Four types of symmetries are considered, and each architecture is explored and implemented using the proposed DA approach. Finally, all these filter structures are integrated by considering a common memory module and a control logic. Memory reuse and sharing are made possible by the FB design, which also allows for parallel processing. The suggested FB design has low resource requirements in terms of both memory and processing power. The hardware utilization synthesis summary is assessed for the target device of the Field Programmable Gate Array (FPGA). After that, the design is synthesized in 45 nm CMOS technology using Cadence's Genus tools for ASIC design. Existing 2-D FIR filter designs and traditional multiplier-based filter architectures are analyzed in terms of area, latency, and PC reports. The proposed FB architecture achieves up to 98.04% reduction in ADP and up to 64.51% reduction in PDP compared to existing designs, highlighting its efficiency in both area and power optimization. The proposed work's layout is then provided, including the Innovus tools used to determine the place and route.</div></div>","PeriodicalId":50630,"journal":{"name":"Computers & Electrical Engineering","volume":"131 ","pages":"Article 110941"},"PeriodicalIF":4.9,"publicationDate":"2026-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145978306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comprehensive analysis of the state of art on emotion recognition using EEG 基于脑电图的情绪识别研究现状综合分析

IF 4.9 3区计算机科学 Q1 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Computers & Electrical Engineering

Pub Date : 2026-01-16 DOI: 10.1016/j.compeleceng.2026.110958

Anju Mishra , Priya Ranjan

Emotion recognition from physiological signals is an emerging field due to its vast application areas. The electroencephalogram (EEG) as a physiological marker in developing automated emotion recognition systems is gaining popularity with its ability to capture the brain's electrical activity providing a window into understanding how these emotional states are represented and processed. Because of this inherent capability of EEG recordings, this systematic review intends to give the readers a comprehensive understanding of the state of the art of the emotion recognition domain and the tools and technologies used by other contemporary researchers in this field. The review outlines the latest research in the field and also performs a comprehensive analysis of available literature to identify the best tools and technologies used by researchers in the domain at every step of the development of such models. The final section of the review tries to point out some directions that can be worked out in the future by the researchers.

基于生理信号的情绪识别是一个新兴的领域，有着广阔的应用领域。脑电图（EEG）作为开发自动情绪识别系统的一种生理标记物越来越受欢迎，因为它能够捕捉大脑的电活动，为理解这些情绪状态是如何表征和处理的提供了一个窗口。由于脑电图记录的这种固有能力，本系统综述旨在让读者全面了解情绪识别领域的最新技术，以及该领域其他当代研究人员使用的工具和技术。该综述概述了该领域的最新研究，并对现有文献进行了全面分析，以确定该领域研究人员在开发此类模型的每一步中使用的最佳工具和技术。评论的最后一部分试图指出研究人员未来可以制定的一些方向。

引用次数: 0

A review of multimodal sentiment analysis: Taxonomy, issues, challenges, and future perspectives 多模态情感分析综述：分类、问题、挑战和未来展望

IF 4.9 3区计算机科学 Q1 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Computers & Electrical Engineering

Pub Date : 2026-01-16 DOI: 10.1016/j.compeleceng.2026.110959

Khalid Anwar, Shreya, Meghna Sharma, Kritika Saanvi

Recent developments in computational intelligence have produced a huge volume of multimodal data across different digital platforms. This data is a great source of contextual, sentimental, and emotional information. Multimodal sentiment analysis (MMSA) is the process of inferring sentiments from multimodal data. MMSA has improved the effectiveness and accuracy of sentiment analysis by integrating heterogeneous modalities. However, there are several issues and challenges in combining multiple modalities, like high complexity, modality fusion, lack of explainability, and temporal synchronization. This paper presents a review of MMSA, discussing data modalities, fusion approaches, issues and challenges. It also presents the statistical analysis and overview of datasets and evaluation metrics used in the reviewed papers. Moreover, it identifies several future research opportunities for the research advancements in MMSA. It is believed that the article will be beneficial for the researchers working in the relevant field.

计算智能的最新发展已经在不同的数字平台上产生了大量的多模态数据。这些数据是上下文、情感和情感信息的重要来源。多模态情感分析（MMSA）是从多模态数据中推断情感的过程。MMSA通过整合异构模式提高了情感分析的有效性和准确性。然而，在多模态组合中存在一些问题和挑战，如高复杂性、模态融合、缺乏可解释性和时间同步。本文介绍了MMSA的综述，讨论了数据模式、融合方法、问题和挑战。它还介绍了数据集的统计分析和概述，以及在审查论文中使用的评估指标。此外，它还确定了MMSA研究进展的几个未来研究机会。相信本文将对相关领域的研究人员有所裨益。

引用次数: 0