Polynomial Neural Barrier Certificate Synthesis of Hybrid Systems via Counterexample Guidance

IF 2.9 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-11-06 DOI:10.1109/TCAD.2024.3447226
Hanrui Zhao;Banglong Liu;Lydia Dehbi;Huijiao Xie;Zhengfeng Yang;Haifeng Qian
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Abstract

This article presents a novel approach to the safety verification of hybrid systems by synthesizing neural barrier certificates (BCs) via counterexample-guided neural network (NN) learning combined with sum-of-square (SOS)-based verification. We learn more easily verifiable BCs with NN polynomial expansions in a high-accuracy counterexamples guided framework. By leveraging the polynomial candidates yielded from the learning phase, we reformulate the identification of real BCs as convex linear matrix inequality (LMI) feasibility testing problems, instead of directly solving the inherently NP-hard nonconvex bilinear matrix inequality (BMI) problems associated with SOS-based BC generation. Furthermore, we decompose the large SOS verification programming into several manageable subprogrammings. Benefiting from the efficiency and scalability advantages, our approach can synthesize BCs not amenable to existing methods and handle more general hybrid systems.
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通过反例指导合成混合系统的多项式神经障碍证书
本文介绍了一种新颖的混合系统安全验证方法,即通过反例引导的神经网络(NN)学习,结合基于平方和(SOS)的验证,合成神经屏障证书(BC)。我们在一个高精度反例引导框架中,利用神经网络多项式展开学习更容易验证的 BC。通过利用学习阶段产生的多项式候选数,我们将实际 BC 的识别重新表述为凸线性矩阵不等式(LMI)可行性测试问题,而不是直接解决与基于 SOS 的 BC 生成相关的固有 NP-困难非凸双线性矩阵不等式(BMI)问题。此外,我们还将庞大的 SOS 验证编程分解为多个易于管理的子程序。得益于效率和可扩展性优势,我们的方法可以合成现有方法无法合成的 BC,并处理更通用的混合系统。
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来源期刊
CiteScore
5.60
自引率
13.80%
发文量
500
审稿时长
7 months
期刊介绍: The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.
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