TCAD simulation of sub-10 nm high-k SOI GaN FinFET by implementing fin optimization approach for high-performance applications

Abstract

This paper reports, the enhanced electrical parameters of sub-10 nm High-k SOI GaN FinFET by implementing fin optimization approach using TCAD simulation. The results show that as the fin aspect ratio (AR) increases, keeping the channel cross-sectional area constant, the static and analog performance of the suggested device enhances. On current of 0.15 mA, higher switching ratio (I_ON/I_OFF) ratio (1.74 × 10⁹), reduced subthreshold swing (by 20%), and higher intrinsic gain has achieved for High-k SOI GaN FinFET having a higher fin AR (3.75) as compared to the lower fin aspect ratio (1.67) owing to the significant reduction in short channel effects. For more insight into the static/analog performances of the device; some other parameters such as transconductance (g_m), energy band profile, surface potential, output conductance (g_d), output resistance (R_o), and early voltage have also been investigated under fin optimization approach (fin aspect ratio modulation). Thus, the enhanced static/analog performances of the High-k SOI GaN FinFET clear the way for RFIC design.