Dhruve A. Ringwala;Matthew A. Mircovich;Manuel A. Roldan;John Kouvetakis;José Menéndez
{"title":"Simplified Designs of Ge1-ySny/Si(100) Diodes for Facile Integration With Si Technologies: Synthesis, Electrical Performance and Modeling Studies","authors":"Dhruve A. Ringwala;Matthew A. Mircovich;Manuel A. Roldan;John Kouvetakis;José Menéndez","doi":"10.1109/JSTQE.2024.3494541","DOIUrl":null,"url":null,"abstract":"This paper describes the properties of \n<italic>pin</i>\n Ge\n<sub>1-</sub>\n<italic><sub>y</sub></i>\nSn\n<italic><sub>y</sub></i>\n diodes (\n<italic>y</i>\n = 4.4-10% Sn) grown directly on Si(100) wafers as a way to investigate the impact of eliminating the Ge buffer layers used conventionally for the integration of GeSn devices on Si. The technology offers a simplified and potentially lower-cost alternative for SWIR-LWIR applications. Two device designs are discussed. The first design adopts a layer sequence \n<italic>n</i>\n-Ge\n<sub>1-</sub>\n<italic><sub>y</sub></i>\nSn\n<italic><sub>y</sub></i>\n/\n<italic>i</i>\n-Ge\n<sub>1-</sub>\n<italic><sub>y</sub></i>\nSn\n<italic><sub>y</sub></i>\n/\n<italic>p</i>\n-Ge\n<sub>1-</sub>\n<italic><sub>y</sub></i>\nSn\n<italic><sub>y</sub></i>\n/Si, featuring a single defected bottom interface between the \n<italic>p</i>\n layer and the Si wafer. This was followed by an even simpler \n<italic>n</i>\n-Ge\n<sub>1-</sub>\n<italic><sub>y</sub></i>\nSn\n<italic><sub>y</sub></i>\n/\n<italic>i</i>\n-Ge\n<sub>1-</sub>\n<italic><sub>y</sub></i>\nSn\n<italic><sub>y</sub></i>\n /\n<italic>p</i>\n-Si heterostructure design. In both cases, the top \n<italic>i</i>\n/\n<italic>n</i>\n interface is pseudomorphic and potentially defect-free. The Ge\n<sub>1-y</sub>\nSn\n<sub>y</sub>\n layers are produced by CVD reactions of Ge\n<sub>3</sub>\nH\n<sub>8</sub>\n and SnH\n<sub>4</sub>\n at temperatures ranging from 290 °C to 300 °C. The \n<italic>n</i>\n-type electrodes in the samples were doped with As using As(SiH\n<sub>3</sub>\n)\n<sub>3</sub>\n, and the \n<italic>p</i>\n-type GeSn layers were doped using diborane as the source of B-atoms. All samples were characterized by XRD, RBS, IR-ellipsometry, AFM and TEM. The layers were found to be monocrystalline single-phase alloys exhibiting mostly relaxed strain states and top surfaces devoid of the cross-hatch surface patterns that are typical of Ge\n<sub>1-</sub>\n<italic><sub>y</sub></i>\nSn\n<italic><sub>y</sub></i>\n films grown on Ge buffers. Current-voltage \n<italic>I-V</i>\n curves of fabricated devices over the 4.4-10% Sn range of interest showed that rectifying behavior is readily attained. It appears that the effect of eliminating the Ge-buffer is an increase of only one order magnitude in the density of defects responsible for the dark current, together with an increase in residual doping in the nominally intrinsic layer. The results suggest that these deleterious effects may be further reduced with improved sample designs, particularly at high Sn-concentrations, opening up new alternatives for the effective integration of GeSn- and Si technologies.","PeriodicalId":13094,"journal":{"name":"IEEE Journal of Selected Topics in Quantum Electronics","volume":"31 1: SiGeSn Infrared Photon. and Quantum Electronics","pages":"1-10"},"PeriodicalIF":4.3000,"publicationDate":"2024-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Selected Topics in Quantum Electronics","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10747390/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This paper describes the properties of
pin
Ge
1-y
Sn
y
diodes (
y
= 4.4-10% Sn) grown directly on Si(100) wafers as a way to investigate the impact of eliminating the Ge buffer layers used conventionally for the integration of GeSn devices on Si. The technology offers a simplified and potentially lower-cost alternative for SWIR-LWIR applications. Two device designs are discussed. The first design adopts a layer sequence
n
-Ge
1-y
Sn
y
/
i
-Ge
1-y
Sn
y
/
p
-Ge
1-y
Sn
y
/Si, featuring a single defected bottom interface between the
p
layer and the Si wafer. This was followed by an even simpler
n
-Ge
1-y
Sn
y
/
i
-Ge
1-y
Sn
y
/
p
-Si heterostructure design. In both cases, the top
i
/
n
interface is pseudomorphic and potentially defect-free. The Ge
1-y
Sn
y
layers are produced by CVD reactions of Ge
3
H
8
and SnH
4
at temperatures ranging from 290 °C to 300 °C. The
n
-type electrodes in the samples were doped with As using As(SiH
3
)
3
, and the
p
-type GeSn layers were doped using diborane as the source of B-atoms. All samples were characterized by XRD, RBS, IR-ellipsometry, AFM and TEM. The layers were found to be monocrystalline single-phase alloys exhibiting mostly relaxed strain states and top surfaces devoid of the cross-hatch surface patterns that are typical of Ge
1-y
Sn
y
films grown on Ge buffers. Current-voltage
I-V
curves of fabricated devices over the 4.4-10% Sn range of interest showed that rectifying behavior is readily attained. It appears that the effect of eliminating the Ge-buffer is an increase of only one order magnitude in the density of defects responsible for the dark current, together with an increase in residual doping in the nominally intrinsic layer. The results suggest that these deleterious effects may be further reduced with improved sample designs, particularly at high Sn-concentrations, opening up new alternatives for the effective integration of GeSn- and Si technologies.
期刊介绍:
Papers published in the IEEE Journal of Selected Topics in Quantum Electronics fall within the broad field of science and technology of quantum electronics of a device, subsystem, or system-oriented nature. Each issue is devoted to a specific topic within this broad spectrum. Announcements of the topical areas planned for future issues, along with deadlines for receipt of manuscripts, are published in this Journal and in the IEEE Journal of Quantum Electronics. Generally, the scope of manuscripts appropriate to this Journal is the same as that for the IEEE Journal of Quantum Electronics. Manuscripts are published that report original theoretical and/or experimental research results that advance the scientific and technological base of quantum electronics devices, systems, or applications. The Journal is dedicated toward publishing research results that advance the state of the art or add to the understanding of the generation, amplification, modulation, detection, waveguiding, or propagation characteristics of coherent electromagnetic radiation having sub-millimeter and shorter wavelengths. In order to be suitable for publication in this Journal, the content of manuscripts concerned with subject-related research must have a potential impact on advancing the technological base of quantum electronic devices, systems, and/or applications. Potential authors of subject-related research have the responsibility of pointing out this potential impact. System-oriented manuscripts must be concerned with systems that perform a function previously unavailable or that outperform previously established systems that did not use quantum electronic components or concepts. Tutorial and review papers are by invitation only.