Enhancing Selector-Only Memory Reliability Through Multi-Step Write Pulse

Abstract

In this study, we investigated the impact of overshoot current (Iover) on the reliability of selector-only memory (SOM) devices based on an ovonic threshold switch (OTS). We found that implementing a multi-step pulse during the write operation reduced Iover by 40%, significantly decreased threshold voltage (Vth) variability during the read process to ensure sufficient read window margin, and improved endurance by more than an order of magnitude, compared to the traditional square pulse. Our analysis revealed that the Iover leads to increased Ion variability, which in turn causes greater variability in the write pulse’s impact on subsequent read process. Furthermore, Iover generates extra injection charge, which directly correlating with increased device stress and significantly impacting endurance. Through intermittent and continuous pulse measurements, we confirmed the critical role of Iover in cycling stability. Our findings underscore the importance of suppressing Iover to enhance SOM reliability, emphasizing the need for optimizing the multi-step pulse method.