Hi-NeRF: A Multicore NeRF Accelerator With Hierarchical Empty Space Skipping for Edge 3-D Rendering

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-24 DOI:10.1109/TVLSI.2024.3458032
Lizhou Wu;Haozhe Zhu;Jiapei Zheng;Mengjie Li;Yinuo Cheng;Qi Liu;Xiaoyang Zeng;Chixiao Chen
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Abstract

Neural radiance field (NeRF) has proved to be promising in augmented/virtual-reality applications. However, the deployment of NeRF on edge devices suffers from inadequate throughput due to redundant ray sampling and congested memory access. To address these challenges, this article proposes Hi-NeRF, a multirendering-core accelerator for efficient edge NeRF rendering. On the architecture level, a hierarchical empty space skipping (HESS) scheme is adopted, which efficiently locates the effective samples with fewer skipping steps and thus accelerates the ray marching process. Furthermore, to alleviate the memory access bottleneck, a vertex-interleaved mapping (VIM) method that eliminates memory bank conflicts is also proposed. On the hardware level, ineffective sample filters (ISFs) and voxel access filters (VCFs) are introduced to further exploit spatial sparsity and data locality at run-time. The experimental results show that our work achieves $2.67\times $ rendering throughput and $11.2\times $ energy efficiency compared to a SOTA NeRF rendering accelerator. The energy efficiency can be improved by $561\times $ compared to a commercial GPU.
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Hi-NeRF:为边缘三维渲染设计的多核 NeRF 加速器与分层空跳频
事实证明,神经辐射场(NeRF)在增强/虚拟现实应用中大有可为。然而,在边缘设备上部署 NeRF 会因冗余光线采样和拥塞的内存访问而导致吞吐量不足。为了应对这些挑战,本文提出了用于高效边缘 NeRF 渲染的多渲染内核加速器 Hi-NeRF。在架构层面,采用了分层空跳转(HESS)方案,以更少的跳转步骤有效定位有效样本,从而加速光线行进过程。此外,为了缓解内存访问瓶颈,还提出了一种消除内存库冲突的顶点交错映射(VIM)方法。在硬件层面,引入了无效采样滤波器(ISF)和体素访问滤波器(VCF),以进一步利用运行时的空间稀疏性和数据局部性。实验结果表明,与SOTA NeRF渲染加速器相比,我们的工作实现了2.67倍的渲染吞吐量和11.2倍的能效。与商用 GPU 相比,能效可提高 561 美元。
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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