Beyond 200-Gb/s PAM4 ADC and DAC-Based Transceiver for Wireline and Linear Optics Applications

Abstract

System considerations, circuit architecture, and design implementation of wireline and linear optics transceivers capable of supporting data-rates beyond 200 Gb/s are presented. We showcase the silicon results of a transceiver designed in the advanced 3-nm CMOS process, which supports long-reach channels with up to 40 dB of loss at Nyquist. These results demonstrate the technology’s benefits of doubling the data rate of transceivers while achieving efficiency gains in power consumption and silicon area. This article highlights several key circuits architecture, such as hybrid continuous-time linear equalizer, inductive peaking clock routing, and one stage TX driver based on grounded switches. The proof-of-concept demonstration of 224 Gb/s with linear optics opens the avenue for power-efficient, low-latency future optical communication. This is crucial for high-performance computing (HPC) networking as well as emerging applications in high-end FPGA.