Design Techniques for Single-Ended Wireline Crosstalk Cancellation Receiver Up To 112 Gb/s

Liping Zhong;Quan Pan
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Abstract

The increasing demand for bandwidth in data centers is driving the advancement of wireline receivers to support higher data rates, even up to 224 Gb/s. A single-ended scheme, which utilizes two single-ended signals on a pair of differential channels, offers a promising solution for achieving this goal. This approach effectively doubles the data throughput of the links and reduces the bandwidth requirements for both active and passive components. However, this scheme suffers from severe crosstalk, especially far-end crosstalk (FEXT). At higher data rates, single-ended crosstalk cancellation interfaces encounter several issues. First, FEXT noise becomes more pronounced at higher frequencies. Additionally, the increased bandwidth demands lead to higher power consumption. Finally, as frequency increases, the channel exhibits severe insertion loss, intensifying the equalization burden on receivers. This article introduces several techniques that enable single-ended crosstalk cancellation receivers to achieve data rates of up to 56 and 112 Gb/s per lane using four-level pulse amplitude modulation (PAM-4) in 28-nm CMOS technology. These 56 and 112 Gb/s receivers achieve a bit error rate of < $10{^{-}10 }$ and < $10{^{-}12 }$ with a single-ended channel loss of 24 and 25 dB, respectively.
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高达112gb /s的单端有线串扰对消接收机设计技术
数据中心对带宽日益增长的需求正在推动有线接收器的发展,以支持更高的数据速率,甚至高达224 Gb/s。单端方案利用一对差分信道上的两个单端信号,为实现这一目标提供了一个有希望的解决方案。这种方法有效地将链路的数据吞吐量提高了一倍,并降低了有源和无源组件的带宽要求。然而,该方案存在严重的串扰,特别是远端串扰(ext)。在较高的数据速率下,单端串扰消除接口会遇到几个问题。首先,文本噪声在更高的频率下变得更加明显。此外,带宽需求的增加会导致更高的功耗。最后,随着频率的增加,信道表现出严重的插入损耗,加重了接收机的均衡负担。本文介绍了几种技术,这些技术使单端串扰消除接收器使用28纳米CMOS技术中的四电平脉冲幅度调制(PAM-4)实现每通道高达56和112 Gb/s的数据速率。这些56和112 Gb/s接收器的误码率分别为$10{^{-}10}$和$10{^{-}12}$,单端信道损耗分别为24和25 dB。
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2025 Index IEEE Open Journal of the Solid-State Circuits Society Vol. 5 New Associate Editors Special Section on Energy-Efficient Biomedical Systems and Circuits Special Section on Temperature Resilient Systems and Circuits Special Section on Chiplet Interconnects and Architectures
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