{"title":"Design Techniques for Single-Ended Wireline Crosstalk Cancellation Receiver Up To 112 Gb/s","authors":"Liping Zhong;Quan Pan","doi":"10.1109/OJSSCS.2024.3502315","DOIUrl":null,"url":null,"abstract":"The increasing demand for bandwidth in data centers is driving the advancement of wireline receivers to support higher data rates, even up to 224 Gb/s. A single-ended scheme, which utilizes two single-ended signals on a pair of differential channels, offers a promising solution for achieving this goal. This approach effectively doubles the data throughput of the links and reduces the bandwidth requirements for both active and passive components. However, this scheme suffers from severe crosstalk, especially far-end crosstalk (FEXT). At higher data rates, single-ended crosstalk cancellation interfaces encounter several issues. First, FEXT noise becomes more pronounced at higher frequencies. Additionally, the increased bandwidth demands lead to higher power consumption. Finally, as frequency increases, the channel exhibits severe insertion loss, intensifying the equalization burden on receivers. This article introduces several techniques that enable single-ended crosstalk cancellation receivers to achieve data rates of up to 56 and 112 Gb/s per lane using four-level pulse amplitude modulation (PAM-4) in 28-nm CMOS technology. These 56 and 112 Gb/s receivers achieve a bit error rate of <\n<inline-formula> <tex-math>$10{^{-}10 }$ </tex-math></inline-formula>\n and <\n<inline-formula> <tex-math>$10{^{-}12 }$ </tex-math></inline-formula>\n with a single-ended channel loss of 24 and 25 dB, respectively.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"318-327"},"PeriodicalIF":0.0000,"publicationDate":"2024-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10757331","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Open Journal of the Solid-State Circuits Society","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10757331/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The increasing demand for bandwidth in data centers is driving the advancement of wireline receivers to support higher data rates, even up to 224 Gb/s. A single-ended scheme, which utilizes two single-ended signals on a pair of differential channels, offers a promising solution for achieving this goal. This approach effectively doubles the data throughput of the links and reduces the bandwidth requirements for both active and passive components. However, this scheme suffers from severe crosstalk, especially far-end crosstalk (FEXT). At higher data rates, single-ended crosstalk cancellation interfaces encounter several issues. First, FEXT noise becomes more pronounced at higher frequencies. Additionally, the increased bandwidth demands lead to higher power consumption. Finally, as frequency increases, the channel exhibits severe insertion loss, intensifying the equalization burden on receivers. This article introduces several techniques that enable single-ended crosstalk cancellation receivers to achieve data rates of up to 56 and 112 Gb/s per lane using four-level pulse amplitude modulation (PAM-4) in 28-nm CMOS technology. These 56 and 112 Gb/s receivers achieve a bit error rate of <
$10{^{-}10 }$
and <
$10{^{-}12 }$
with a single-ended channel loss of 24 and 25 dB, respectively.