Hang Xu;Jianbin Guo;Tianyang Feng;Yafen Yang;David Wei Zhang
{"title":"Comparative Analysis of SGTMOS Degradation Under Repeated Off-State Avalanche and Short Circuit Current Pulses","authors":"Hang Xu;Jianbin Guo;Tianyang Feng;Yafen Yang;David Wei Zhang","doi":"10.1109/TDMR.2024.3467096","DOIUrl":null,"url":null,"abstract":"In this article, a 60-V split-gate trench vertical double diffused metal-oxide-semiconductor field-effect transistor (SGTVDMOS, SGTMOS) with low on-resistance is designed and manufactured. The device adopts an ultra-deep split gate trench with a grounded bottom shield gate. The electrical parameters degradations subsequent to repeated off-state avalanche and short circuit current pulses are investigated and compared for the first time. After avalanche voltage stress, crucial parameters such as threshold voltage (Vt), Miller capacitance (CGD) remain unaffected. However, a noteworthy change is observed in blocking characteristics, manifested as an increase in breakdown voltage. Conversely, after subjecting the device to short-circuit pulse current stress, a minor reduction in \n<inline-formula> <tex-math>$\\rm V_{t}$ </tex-math></inline-formula>\n is noted, while the breakdown characteristics remain constant. Technology computer-aided design (TCAD) simulation and actual test analysis are combined to reveal the degradation mechanism, it has been determined that electron injection degradation occurs under both stresses. However, distinct degradation phenomena occur due to the disparate positions of electron injection. During avalanche stress, electrons within the polysilicon (shield gate) tunnel into the oxide layer of the bottom shielding gate, while hot electron injection occurs near the active trench gate during a continuous short-circuit pulses.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"596-601"},"PeriodicalIF":2.5000,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Device and Materials Reliability","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10690173/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
In this article, a 60-V split-gate trench vertical double diffused metal-oxide-semiconductor field-effect transistor (SGTVDMOS, SGTMOS) with low on-resistance is designed and manufactured. The device adopts an ultra-deep split gate trench with a grounded bottom shield gate. The electrical parameters degradations subsequent to repeated off-state avalanche and short circuit current pulses are investigated and compared for the first time. After avalanche voltage stress, crucial parameters such as threshold voltage (Vt), Miller capacitance (CGD) remain unaffected. However, a noteworthy change is observed in blocking characteristics, manifested as an increase in breakdown voltage. Conversely, after subjecting the device to short-circuit pulse current stress, a minor reduction in
$\rm V_{t}$
is noted, while the breakdown characteristics remain constant. Technology computer-aided design (TCAD) simulation and actual test analysis are combined to reveal the degradation mechanism, it has been determined that electron injection degradation occurs under both stresses. However, distinct degradation phenomena occur due to the disparate positions of electron injection. During avalanche stress, electrons within the polysilicon (shield gate) tunnel into the oxide layer of the bottom shielding gate, while hot electron injection occurs near the active trench gate during a continuous short-circuit pulses.
期刊介绍:
The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.