Comparative Analysis of SGTMOS Degradation Under Repeated Off-State Avalanche and Short Circuit Current Pulses

IF 2.5 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-24 DOI:10.1109/TDMR.2024.3467096
Hang Xu;Jianbin Guo;Tianyang Feng;Yafen Yang;David Wei Zhang
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Abstract

In this article, a 60-V split-gate trench vertical double diffused metal-oxide-semiconductor field-effect transistor (SGTVDMOS, SGTMOS) with low on-resistance is designed and manufactured. The device adopts an ultra-deep split gate trench with a grounded bottom shield gate. The electrical parameters degradations subsequent to repeated off-state avalanche and short circuit current pulses are investigated and compared for the first time. After avalanche voltage stress, crucial parameters such as threshold voltage (Vt), Miller capacitance (CGD) remain unaffected. However, a noteworthy change is observed in blocking characteristics, manifested as an increase in breakdown voltage. Conversely, after subjecting the device to short-circuit pulse current stress, a minor reduction in $\rm V_{t}$ is noted, while the breakdown characteristics remain constant. Technology computer-aided design (TCAD) simulation and actual test analysis are combined to reveal the degradation mechanism, it has been determined that electron injection degradation occurs under both stresses. However, distinct degradation phenomena occur due to the disparate positions of electron injection. During avalanche stress, electrons within the polysilicon (shield gate) tunnel into the oxide layer of the bottom shielding gate, while hot electron injection occurs near the active trench gate during a continuous short-circuit pulses.
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重复断态雪崩和短路电流脉冲下SGTMOS退化的比较分析
本文设计并制造了一种低导通电阻的60 v分栅沟槽垂直双扩散金属氧化物半导体场效应晶体管(SGTVDMOS, SGTMOS)。该装置采用带接地底屏蔽栅的超深分栅沟槽。本文首次研究和比较了反复的断态雪崩和短路电流脉冲引起的电学参数退化。雪崩电压应力后,阈值电压(Vt)、米勒电容(CGD)等关键参数不受影响。然而,在阻断特性中观察到一个值得注意的变化,表现为击穿电压的增加。相反,在对器件施加短路脉冲电流应力后,可以注意到$\rm V_{t}$的微小减小,而击穿特性保持不变。通过计算机辅助设计(TCAD)仿真和实际试验分析相结合,揭示了降解机理,确定了两种应力下均发生电子注入降解。然而,由于电子注入的位置不同,会产生明显的降解现象。在雪崩应力下,多晶硅(屏蔽栅)内的电子隧穿到底部屏蔽栅的氧化层中,而在连续短路脉冲期间,在活动沟槽栅附近发生热电子注入。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Transactions on Device and Materials Reliability
IEEE Transactions on Device and Materials Reliability 工程技术-工程:电子与电气
CiteScore
4.80
自引率
5.00%
发文量
71
审稿时长
6-12 weeks
期刊介绍: The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.
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