The Failure Mechanism of Internal Circuit During ESD Striking a Power to Another Power

Abstract

Although power supply stressed with respect to another supply is one test items of the electrostatic-discharge (ESD) qualification. However, a current path still exists that has not been reported earlier. From the failure analysis result, the damage is located at the high-voltage N-Well (HVNW) guard-ring of the zapped power domain. Based on the TCAD simulation, the failure mechanism is identified, and shows good agreement with silicon. It proves that the ESD current can only flow through the internal circuit of the zapped power domain and P+ guard-ring (VSS) to become a quiescent current before the power clamp device turns on. So, the internal circuit of the zapped power domain and P+ guard-ring become a substrate triggering circuit to turn on the parasitic npn bipolar between two different power domains, resulting in most ESD current flowing through HVNW guard-rings to induce the damage.