A 59.6fsrms Jitter Sub-Sampling PLL With Foreground Open-Loop Gain Calibration

Abstract

A sub-sampling phase-locked loop (SSPLL) with foreground open-loop gain calibration is presented. By digitally adjusting the transconductance cell, the open-loop gain of the SSPLL is calibrated. This SSPLL is fabricated in 40 nm CMOS technology. Its active area is $0.167~{\mathrm { mm}}^{2}$ and the power consumption is 14.08mW at 6.4 GHz for a supply of 1V. The root-mean-square (RMS) jitter is 59.6fs while the phase noise is integrated with the offset frequency from 1 kHz to 100MHz. The calculated figure of merit is −253dB. With the calibration, the maximal deviation of the loop bandwidth is reduced from −41.5% to −7.3% for the supply voltage of 0.9V~1.1V. The maximal deviation of the RMS jitter is reduced from 23.6% to 4.7%. For five chips, the maximal deviation of the loop bandwidth is reduced from −34.9% to 4% with calibration. And the maximal deviation of the RMS jitter is reduced from 10.9% to −3.4%.