{"title":"A Balanced Power Amplifier With Complementary Adaptive Bias in 28-nm Bulk CMOS for 5G Millimeter-Wave Systems","authors":"Ning-Zheng Sun;Li Gao;Weisen Zeng;Jie Hu;Xinyang Liu;Xiu Yin Zhang","doi":"10.1109/TCSII.2024.3480706","DOIUrl":null,"url":null,"abstract":"This brief presents a balanced power amplifier (BPA) with adaptive-bias for 5G applications based on 28-nm bulk CMOS process. The PA utilizes a differential balanced structure which cancels out reflected signals at the isolation ports, thereby improving return losses. A folded differential quadrature coupler is designed to connect respectively to the input and output of the PAs. The folded layout effectively reduces the chip size. In addition, a complementary adaptive bias is implemented to cancel out the nonlinear effects of the two PAs, significantly enhancing the overall linearity. The measure PA realizes a 3-dB bandwidth of \n<inline-formula> <tex-math>$21.3\\sim 28$ </tex-math></inline-formula>\n.4 GHz with a peak gain of 21.1 dB. The large-signal measurement results show that the PA achieve an OP1dB of 20.3 dBm, a \n<inline-formula> <tex-math>$P_{\\mathrm { sat}}$ </tex-math></inline-formula>\n of 21.6 dBm, and a peak PAE (PAEmax) of 30.9%. The measured |AM-PM|P1dB is less than 8.9°, which is \n<inline-formula> <tex-math>$3\\sim 8^{\\circ }$ </tex-math></inline-formula>\n lower than when using a normal bias. For 5G NR FR2 200-MHz 64QAM signals, the measured \n<inline-formula> <tex-math>$P_{\\mathrm { avg}}$ </tex-math></inline-formula>\n / \n<inline-formula> <tex-math>${\\mathrm { PAE}}_{\\mathrm { avg}}$ </tex-math></inline-formula>\n / ACPR of 11.2 dBm / 6% / –24.9 dBc are achieved at the EVM of –25 dB. The DC power supply voltage is 1.8 V. The core chip size is only 0.27 mm2, demonstrating a compact design within a balanced architecture.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"58-62"},"PeriodicalIF":4.0000,"publicationDate":"2024-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems II: Express Briefs","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10716542/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This brief presents a balanced power amplifier (BPA) with adaptive-bias for 5G applications based on 28-nm bulk CMOS process. The PA utilizes a differential balanced structure which cancels out reflected signals at the isolation ports, thereby improving return losses. A folded differential quadrature coupler is designed to connect respectively to the input and output of the PAs. The folded layout effectively reduces the chip size. In addition, a complementary adaptive bias is implemented to cancel out the nonlinear effects of the two PAs, significantly enhancing the overall linearity. The measure PA realizes a 3-dB bandwidth of
$21.3\sim 28$
.4 GHz with a peak gain of 21.1 dB. The large-signal measurement results show that the PA achieve an OP1dB of 20.3 dBm, a
$P_{\mathrm { sat}}$
of 21.6 dBm, and a peak PAE (PAEmax) of 30.9%. The measured |AM-PM|P1dB is less than 8.9°, which is
$3\sim 8^{\circ }$
lower than when using a normal bias. For 5G NR FR2 200-MHz 64QAM signals, the measured
$P_{\mathrm { avg}}$
/
${\mathrm { PAE}}_{\mathrm { avg}}$
/ ACPR of 11.2 dBm / 6% / –24.9 dBc are achieved at the EVM of –25 dB. The DC power supply voltage is 1.8 V. The core chip size is only 0.27 mm2, demonstrating a compact design within a balanced architecture.
期刊介绍:
TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:
Circuits: Analog, Digital and Mixed Signal Circuits and Systems
Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
Circuits and Systems, Power Electronics and Systems
Software for Analog-and-Logic Circuits and Systems
Control aspects of Circuits and Systems.