{"title":"A Novel NN-Based Fast-Convergence Background Calibration for Timing Mismatch in TI ADCs","authors":"Zhifei Lu;Boyuan Zhang;Yutao Peng;Xizhu Peng;He Tang;Jie Pu;Ling Qin;Mingqiang Guo","doi":"10.1109/TCSII.2024.3477463","DOIUrl":null,"url":null,"abstract":"A novel background calibration technique for timing mismatch in time-interleaved ADCs (TI ADCs) with fast convergence speed is presented in this brief. The proposed calibration applies a customized neural network (NN) to extract the information of timing skews for compensation. Compared to the conventional background methods for calibrating timing mismatches without reference, this brief significantly increases the convergence speed with high accuracy. In comparison with prior NN-based calibration works, this brief could follow the error changes in the background and has stronger robustness, also without any risk of fidelity problem. A 12-bit 3GSps 4-channel TI ADC model with noise and jitter is simulated for verifying the effectiveness of this technique. Simulation results show that the proposed technique could improve the SNDR and SFDR by 7.41dB and 24.73dB respectively, with only 1536 samples for convergence. Off-chip validation with a 12-bit 3GSps 4-channel TI ADC also proves the effectiveness and practicality of this brief.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"48-52"},"PeriodicalIF":4.0000,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems II: Express Briefs","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10713450/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
A novel background calibration technique for timing mismatch in time-interleaved ADCs (TI ADCs) with fast convergence speed is presented in this brief. The proposed calibration applies a customized neural network (NN) to extract the information of timing skews for compensation. Compared to the conventional background methods for calibrating timing mismatches without reference, this brief significantly increases the convergence speed with high accuracy. In comparison with prior NN-based calibration works, this brief could follow the error changes in the background and has stronger robustness, also without any risk of fidelity problem. A 12-bit 3GSps 4-channel TI ADC model with noise and jitter is simulated for verifying the effectiveness of this technique. Simulation results show that the proposed technique could improve the SNDR and SFDR by 7.41dB and 24.73dB respectively, with only 1536 samples for convergence. Off-chip validation with a 12-bit 3GSps 4-channel TI ADC also proves the effectiveness and practicality of this brief.
期刊介绍:
TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:
Circuits: Analog, Digital and Mixed Signal Circuits and Systems
Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
Circuits and Systems, Power Electronics and Systems
Software for Analog-and-Logic Circuits and Systems
Control aspects of Circuits and Systems.