Energy-Efficient Hybrid Spin-CMOS Logic Design Based on Cascadable Spin-Torque Majority Gate

Abstract

This article proposes a hybrid spin-complementary metal–oxide–semiconductor (CMOS) logic design based on cascadable spin-torque majority gate (STMG), which allows the implementation of multiple STMG logic stages for very large-scale integration circuits by addressing the cascading and fan-out issues encountered in conventional STMGs. In conventional STMG-based logic circuits, excessive current flow occurs owing to simultaneous majority-gate operation across all stages, which may degrade the reliability of domain walls. In contrast, the cascadable STMG (C-STMG), composed of an STMG device and transistors, enables sequential majority gate operations at only selected stages. Furthermore, C-STMG circuits can be segmented into finer stages, enabling fine-grained pipelining, thereby achieving a higher throughput than conventional STMG. Additionally, this article presents a method for designing a 16-bit full-adder (FA) circuit using C-STMG. After the design and verification of the 16-bit C-STMG FA, 32-bit and 64-bit C-STMG FAs are designed, and all configurations are compared with the corresponding CMOS FAs under the same conditions. The C-STMG FAs achieve over 28% improvement in the energy compared with CMOS FAs. Moreover, the improvement in energy consumption is more significant at smaller activity ratios because C-STMG circuits exhibit almost-zero leakage power consumption owing to their non-volatility. In particular, the 64-bit C-STMG FA achieves 76.8% lower-energy dissipation at activity ratios of 1% compared with the corresponding CMOS FA.