Optimization of Asymmetries in Source/Drain Configurations and Tapered Channels for Vertical-Transport Silicon Nanosheet FETs

Abstract

This article presents a thorough investigation of the optimization of asymmetries in vertical-transport nanosheet field-effect transistors (VFETs), considering both asymmetric source/drain (S/D) structures and channel tapering. For asymmetric S/D configurations, n-type FETs (nFETs) exhibit smaller RC delay in the top-source (TopS) configuration, wherein the source has a shorter current path and less voltage drop. Conversely, p-type FETs (pFETs) exhibit smaller RC delay in the bottom-source (BotS) configuration owing to the dominant effect of asymmetric channel stress over the current path difference. Meanwhile, channel tapering significantly affects the optimization of asymmetric VFETs, especially for nFETs. Considering channel tapering, nFET with the smallest RC delay is the BotS configuration, in contrast to the untapered case, whereas BotS configuration is still the optimal structure for pFETs, regardless of the channel tapering. Finally, optimal structures of asymmetric VFETs are presented for various channel widths based on a comparison of the power-delay product (PDP). In nFETs, BotS configuration is optimal for wide channel widths; however, the TopS becomes superior as the channel width decreases in terms of PDP. Meanwhile, optimal structures for pFETs are BotS configurations regardless of the channel tapering and width. For various system-on-chip (SoC) applications, nFETs require a more detailed design than pFETs. Consequently, this study affords comprehensive insights for optimizing VFETs suitable for various applications.