Analysis and Optimization of Burn-In Techniques for Screening Commercial 1.2-kV SiC MOSFETs

Abstract

The burn-in technique is a well-established screening method designed to eliminate early failures in the gate oxide of silicon carbide (SiC) MOSFETs. Despite its widespread application, optimizing the burn-in technique to improve both efficiency and feasibility remains a significant challenge. This study investigates the performance of commercial 1.2-kV SiC planar MOSFETs following the burn-in process, focusing on parameters, such as threshold voltage ( ${V}_{\text {th}}\text {)}$ , on -resistance ( ${R}_{\text {on}}\text {)}$ , and subthreshold hysteresis (Hy). The degradation characteristics of SiC MOSFETs during the burn-in and subsequent recovery processes are thoroughly analyzed. The results indicate that aggressive burn-in conditions, such as elevated oxide electric fields or prolonged stress durations, induce defect generation at or near the SiC/SiO2 interface. These new defects and pre-existing defects promote electron trapping, leading to an increase in ${V}_{\text {th}}$ and ${R}_{\text {on}}$ . Therefore, this study proposes two optimization strategies to refine the burn-in technique while maintaining the intrinsic performance of SiC MOSFETs under demanding conditions. The first approach involves identifying a critical stress duration to minimize defect generation during the burn-in process. The second approach utilizes pulse-mode burn-in technology, incorporating a negative gate bias to reduce the effects of electron trapping.