A Structural Impact Study and Process Optimization of FinFET Parasitic Capacitance

Abstract

While excelling in device density and driving capability, the fin field-effect transistor (FinFET) development has highlighted the increasing impact of parasitic capacitance on high-frequency performance. Here, we report a comprehensive impact study of FinFET structures and key process on the parasitic capacitance, particularly the gate-source/drain (S/D) capacitance ( ${C} _{\text {G-SD}}$ ). By TCAD simulation, the optimal structural parameters of the fin and S/D geometry have been identified with improved dc performance as well as ${C} _{\text {G-SD}}$ characteristics. The parasitic ${C} _{\text {G-SD}}$ is further suppressed by optimized high-k/metal gate (HKMG) critical process steps. Enhanced ac performance is experimentally achieved realizing over 20% improvement in cutoff frequency ( ${f} _{\text {T}}$ ) and maximum oscillation frequency ( ${f} _{\max }$ ) as compared to baseline (320.4-GHz ${f} _{\text {T}}$ and 362.2-GHz ${f} _{\max }$ for nMOS and 393-GHz ${f} _{\text {T}}$ and 168-GHz ${f} _{\max }$ for pMOS). The results demonstrate practical potential in both device-level and circuit-level engineering toward advanced FinFET-based high-frequency applications.