Design Space and Variability Analysis of SOI MOSFET for Ultralow-Power Band-to-Band Tunneling Neurons

IF 2.9 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Electron Devices Pub Date : 2024-12-05 DOI:10.1109/TED.2024.3507758
Jay Sonawane;Shubham Patil;Abhishek Kadam;Ajay Kumar Singh;Sandip Lashkare;Veeresh Deshpande;Udayan Ganguly
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Abstract

Large spiking neural networks (SNNs) require ultralow power and low variability hardware for neuromorphic computing applications. Recently, a band-to-band tunneling (BTBT)-based integrator was proposed, enabling the sub-kHz operation of neurons with area and energy efficiency. For an ultralow-power implementation of such neurons, a very low BTBT current is needed, so minimizing current without degrading neuronal properties is essential. Low variability is needed in the ultralow current integrator to avoid network performance degradation in a large BTBT neuron-based SNN. This work addresses device optimization to achieve low BTBT current. We conducted design space and variability analysis in technology computer-aided design (TCAD), utilizing a well-calibrated TCAD deck with experimental data from GlobalFoundries (GFs) 32 nm partially depleted silicon-on-insulator (PD-SOI) MOSFET. First, we discuss the physics-based explanation of the tunneling mechanism. Second, we explore the impact of device design parameters on SOI MOSFET performance, highlighting parameter sensitivities to tunneling current. With device parameters’ optimization, we demonstrate a $\sim 20\times $ reduction in BTBT current compared to the experimental data. Finally, a variability analysis that includes the effects of random dopant fluctuations (RDFs), oxide thickness variation (OTV), and channel-oxide interface traps ( ${D} _{\text {IT}}$ ) in the BTBT, subthreshold (SS), and ON regimes of operation is shown. The BTBT regime shows the highest sensitivity to OTV, with variability increasing by up to $25\times $ compared to the SS regime. In contrast, RDF and ${D} _{\text {IT}}$ variability resulted in a $1.25\times $ to $\sim 10\times $ lower coefficient of variation (CV) in the BTBT regime than in the SS regime, indicating better resilience to these sources of variability. The study provides essential design guidelines to enable energy-efficient neuromorphic computing, achieving biologically plausible sub-kHz spiking frequencies.
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超低功率带对带隧道神经元SOI MOSFET的设计空间与可变性分析
大型峰值神经网络(snn)需要超低功耗和低可变性的硬件来实现神经形态计算应用。最近,提出了一种基于带到带隧道(BTBT)的积分器,使神经元的亚khz操作具有面积和能量效率。对于这种神经元的超低功耗实现,需要非常低的BTBT电流,因此在不降低神经元特性的情况下最小化电流是必不可少的。在基于BTBT神经元的大型SNN中,超低电流积分器需要低变异性以避免网络性能下降。这项工作解决了器件优化,以实现低BTBT电流。我们在计算机辅助设计(TCAD)技术中进行了设计空间和可变性分析,利用经过校准的TCAD平台和来自GlobalFoundries (GFs) 32纳米部分耗尽绝缘体上硅(PD-SOI) MOSFET的实验数据。首先,我们讨论了隧穿机制的物理解释。其次,我们探讨了器件设计参数对SOI MOSFET性能的影响,重点介绍了参数对隧道电流的敏感性。通过对器件参数的优化,我们证明了与实验数据相比,BTBT电流降低了20倍。最后,对随机掺杂波动(RDFs)、氧化物厚度变化(OTV)和通道-氧化物界面陷阱(${D} _{\text {IT}}$)在BTBT、亚阈值(SS)和ON运行模式下的影响进行了变异性分析。BTBT体系对OTV表现出最高的敏感性,与SS体系相比,其变异性增加了高达25倍。相比之下,RDF和${D} _{text}}$可变性导致BTBT体系的变异系数(CV)比SS体系低1.25倍至10倍,表明BTBT体系对这些变异源有更好的恢复能力。该研究为实现节能的神经形态计算提供了基本的设计指南,实现了生物学上合理的亚千赫峰值频率。
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来源期刊
IEEE Transactions on Electron Devices
IEEE Transactions on Electron Devices 工程技术-工程:电子与电气
CiteScore
5.80
自引率
16.10%
发文量
937
审稿时长
3.8 months
期刊介绍: IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors. Tutorial and review papers on these subjects are also published and occasional special issues appear to present a collection of papers which treat particular areas in more depth and breadth.
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