Controlled Acceleration of PCM Cells Time Drift Through On-Chip Current-Induced Annealing for AIMC Multilevel MVM Computation

Abstract

This article introduces a method to mitigate conductance time drift of phase-change memory (PCM) cells for improved resilience of matrix-vector multiplication (MVM) in analog in-memory computing (AIMC) systems. The proposed approach consists of on-chip current-induced annealing of each PCM device to stabilize its conductance at a target level, avoiding any rearrangement of the cell lattice. The procedure is performed within the programming phase of PCM devices with no severe constraints on execution time because of the infrequent update of MVM weights in deep neural networks (DNNs). Experimental validations were conducted on a 90-nm STMicroelectronics CMOS Ge-rich GeSbTe (GST)-embedded PCM targeting 16 conductance levels, and results indicate that the average time drift and variability of cells conductance are reduced by at least a factor of 2.3 and 3.5, respectively, compared with standard programming. Simulations based on empirical results reveal a 0.8% MVM accuracy loss after 12 h at room temperature and 4.8% after an additional 64-h bake at 85 ° C, with a considerable increase in MVM computing retention compared with those granted with standard programming. Accuracy loss is minimized to around 1% even at high temperatures when the proposed method is combined with hardware drift compensation.