Improved Electrochemical Plating for Void-Free Copper Line in ULSI Interconnect

Abstract

Being the fundamental process of advanced back-end-of-line (BEOL) interconnects, the performance of copper (Cu) electrochemical plating (ECP) affects the resistivity of metal lines and plays a crucial role in RC delay and reliability concerns. A great deal of attention has been focused on reducing the Cu voids, but few reports concentrate on the initial period of ECP, especially when the wafer is immersed in the electrolyte. By optimizing the wafer immersion conditions, I achieved a defect image quantification reduction from a maximum of 88ea to a minimum of 0ea, indicating that a void-free Cu line was realized through a standard plating process, thanks to the reduced surface potential difference during the initial phase. As we develop advanced technology nodes such as below the 7 nm technology node, the higher requirement for the RC delay and reliability performance, this work has good potential applications below the 7 nm technology node, because it provides a promising solution to reduce Cu line voids and can be beneficial to alleviate the RC delay and enhance the reliability in back end of line (BEOL) interconnection.

Graphic Abstract