An Analog Gain Inflection Predistorter for Combined Back-Off Efficiency and Linearity With Doherty Power Amplifiers

Abstract

In this work, a novel tri-branch Doherty analog predistorter (DAPD) for the linearization of gain inflection within Doherty power amplifiers (DPAs) is demonstrated. This proposed circuit topology features two nonlinear branches, which can follow the amplitude and phase characteristic of a DPA in a reverse manner. The first branch conducts whilst the carrier is active in the low power range, whilst both branches conduct when both the carrier and peaking are active in the high power range. A thorough evaluation of this new topology is provided, where the overall gain and phase characteristics of the circuit are mathematically defined. Analysis is provided on various configurations of the topology, where in each case the ability to accurately predistort the gain and phase nonlinearity associated with carrier compression within a DPA is shown. An accurate DAPD design is then detailed, by means of passive modeling, and the use of measured predistortion characteristics of the candidate DPA to be linearized. Measurements are then provided on the combination of the manufactured DAPD with the candidate DPA, through modulated, continuous-wave, and two-tone signal measurements. When considering an orthogonal frequency division multiplexing (OFDM) waveform with varying bandwidths of 20, 50, and 80 MHz, and varying peak-to-average power ratios (PAPRs) of 8.6, 10, and 11.6 dB, a minimum level of adjacent channel power ratio (ACPR) of −40.9 to −43.5 dBc is observed, over a bandwidth of 2.2–2.6 GHz. A minimum error vector magnitude (EVM) of 1.4%–3.8% is also observed, along with a maximum average efficiency of 59.2%–67.5%.