A 36-Gb/s 1.6-pJ/b PAM-3 Transmitter Leveraging Digital Logic Cells and 4-Tap FFE in 22-nm CMOS

Abstract

The first 36-Gb/s transmitter with differential outputs leveraging the three-level pulse amplitude modulation (PAM-3) and digital logic cells is investigated in this study. The employment of digital logic cells simplifies design complexity, enabling the transmitter to achieve an energy efficiency of 1.6pJ/bit under a 1-V supply, and 0.88 pJ/bit when solely considering the data path. The measurement of data rates and energy efficiencies is conducted using an external power supply, omitting an on-chip voltage regulator. The proposed transmitter adopts a 3-bit to 2 unit-intervals (UIs) encoding scheme, considering factors of power consumption, design complexity, area, and bit efficiency. The circuit macro is fabricated in 22nm standard CMOS technology and occupies an area of 0.025mm2 for the transmitter only, and 0.055mm2 for both the transmitter and T-coils. The utilization of 4-tap feedforward equalizer (FFE) yields enhancement in eye opening area, achieving a substantial 96.5% increase at 33Gb/s of data rate and 300% at 34.5Gb/s. The eye measurements are conducted using a pair of 0.914-meter cables.