Robust In-Memory Computation With Bayesian Analog Error Mitigating Codes

Abstract

In-memory computation (IMC) is a promising technology for enabling low-latency and energy-efficient deep learning and artificial intelligence (AI) applications at edge devices. However, the IMC crossbar array, typically implemented using resistive random access memory (RRAM), faces hardware defects that pose a significant challenge to reliable computation. This paper presents a robust IMC scheme utilizing Bayesian neural network-accelerated analog codes. Our approach includes a new datapath design comprising a parity matrix generator and a low-complexity decoder module to facilitate analog codes for IMC. Moreover, we introduce a Gaussian mixture model-based error prior to capture impulsive error statistics and leverage variational Bayesian inference (VBI) techniques for training neural network weights. Extensive simulations confirm the effectiveness of our proposed solution compared to various state-of-the-art baseline schemes.