A 10 W 93.7% peak efficiency load balanced single inductor double output (SIDO) hysteretic buck converter with 0.0063 mV/mA low cross regulation

IF 1.2 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Analog Integrated Circuits and Signal Processing Pub Date : 2025-01-18 DOI:10.1007/s10470-025-02302-6
Seyrani Korkmaz, Gunhan Dundar
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Abstract

This paper presents a novel Single Inductor Double Output (SIDO) Hysteretic Buck converter which balances one output with respect to the other by continously monitoring the load demands of both outputs and then aligning the outputs such that each output regulates its load with minimal disturbance to the other. Load balancing prioritizes the inductor current delivery in the case of a large load current request. The controller aims to finalize the ongoing regulation of the recent output in a prompt manner and then directs the inductor current to the steep load demand output and afterwards returns to the initial output regulation in an iterative way. In conjunction with iterative duty cycle adjustment of outputs, a frequency counter is utilized to accelerate the iteration process to enhance the transient response further. In addition, a delay locked loop fine tunes the duty cycle further to reduce the steady state cross regulation and also limits the switching frequency spectrum. Consequently, both static cross regulation and transient cross regulation performance are further improved compared to previous SIDO architectures. Post-layout simulation results indicate that this architecture has a static cross regulation of 0.0009 mV/mA and transient cross regulation of 0.0063 mV/mA. This SIDO buck converter outperforms the previous studies with a total power delivery capability by supplying 3A load current at each output and 10 W of total power with a peak efficiency of 93.7%.

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一个10瓦93.7%峰值效率负载平衡单电感双输出(SIDO)迟滞降压变换器,0.0063 mV/mA低交叉调节
本文提出了一种新型的单电感双输出(SIDO)滞回Buck变换器,它通过连续监测两个输出的负载需求,然后对齐输出,使每个输出在对另一个输出干扰最小的情况下调节其负载,从而使一个输出相对于另一个输出平衡。负载平衡在大负载电流请求的情况下优先考虑电感电流的输送。控制器的目的是迅速完成对最近输出的持续调节,然后将电感电流定向到陡负载需求输出,然后以迭代的方式返回到初始输出调节。结合输出的迭代占空比调整,利用频率计数器加速迭代过程,进一步提高暂态响应。此外,延时锁紧环进一步微调占空比,以减少稳态交叉调节,并限制开关频谱。因此,与以前的SIDO结构相比,静态交叉调节和瞬态交叉调节性能都得到了进一步提高。布局后仿真结果表明,该结构的静态交叉调节为0.0009 mV/mA,瞬态交叉调节为0.0063 mV/mA。该SIDO降压变换器的总功率输出能力优于以往的研究,在每个输出端提供3A负载电流和10w总功率,峰值效率为93.7%。
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来源期刊
Analog Integrated Circuits and Signal Processing
Analog Integrated Circuits and Signal Processing 工程技术-工程:电子与电气
CiteScore
0.30
自引率
7.10%
发文量
141
审稿时长
7.3 months
期刊介绍: Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today. A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.
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