Noise tolerant and power optimized ternary combinational circuits for arithmetic logic unit

Abstract

This article proposed the use of an efficient ternary multiplexer as a building block in the implementation of ternary adders and multipliers. These designs aim to reduce the power consumption and minimize the transistor counts while maintaining low noise sensitivity. All ternary circuits use carbon nanotube field-effect transistor technology to achieve all levels due to the variable threshold property. The proposed ternary circuits have been evaluated and compared to state-of-the-art designs in the literature using the HSPICE simulator. The average power consumption of the proposed ternary multiplexer has improved up to 95 %. The average power of the proposed ternary half adder is improved by 99 % and the power-delay product of it is reduced up to 99 %. The proposed ternary multiplier and ternary half adder have reduced the transistor count by up to 60 % and 36 % respectively, in comparison to existing designs. The delay of the proposed ternary multiplier and ternary half adder has been reduced by up to 13 % and 93 %, respectively.