Design and parametric characterization of CNTFET based stable static random access memory bit-cell for low-power applications

Abstract

The Carbon Nanotube Field Effect Transistor (CNTFET) is rapidly emerging as an attractive alternative to traditional CMOS transistors. In this work, a stable Feedback Cutting, PPN inverter based 10 transistor (FCPPN10T) Static Random Access Memory (SRAM) bit-cell design based on CNTFETs has been designed for low-power operations. The proposed cell has been tested for key parametric variation of CNTFET transistors such as chiral vector, pitch, number of carbon nonotubes, dielectric constant, and oxide thickness. The proposed FCPPN10T SRAM cell improves read/write static noise margin by 1.98$\times$/ 1.132$\times$, respectively, at 0.3 V compared to conventional 6T SRAM that uses similar CNTFET parameters. The read/write delay of proposed FCPPN10T is higher by 1.03$\times$/ 1.24$\times$, respectively, at 0.3 V compared to conventional 6T SRAM. The leakage power of proposed design is improved by 4.118$\times$ compared to conventional 6T. The proposed design parameters are also compared with three pre-proposed SRAM bit-cells. The simulation is performed with the Cadence Virtuoso using the Stanford University 32 nm CNTFET Verilog model.