Sampling-Based PLLs: A brief overview and tutorial

Abstract

A PLL is one of the most ubiquitous components in modern ICs and often used for clock generation and frequency synthesis. Figure 1 shows a classical PLL architecture. It consists of a VCO locked to a reference clock by a feedback loop with a PFD, a charge pump (CP), a loop filter (LF), and a frequency divider with ratio N (÷N). The RMS jitter ${\sigma}_{t}$ and power consumption P are critical performance parameters for a PLL design.