A High-Reliability, Non-CRP-Discard Arbiter PUF Based on Delay Difference Quantization

IF 5.2 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-10-08 DOI:10.1109/TCSI.2024.3466972
Yao Wang;Guangyang Zhang;Xue Mei;Chongyan Gu
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Abstract

As a lightweight hardware security primitive, physical unclonable functions (PUFs) can provide reliable identity authentication for the Internet of Things (IoT) devices with limited resources. Arbiter PUF (APUF) is one of the most well-known PUF circuits. However, its hardware implementation has poor reliability on field programmable gate arrays (FPGAs). This paper proposed a highly reliable APUF that uses a delay difference quantization strategy (DDQ-APUF). By adding multiple configurable delay units to the two symmetrical paths of the conventional APUF, the delay difference between the two symmetrical paths of APUF can be obtained by collecting the output of APUF under different delay configurations. Compared to conventional APUFs, DDQ-APUF does not use the arbitration result of signal transmission in two symmetric paths as its response, but rather uses the quantified delay difference between the two paths as its response. A tolerance threshold is adopted in the authentication to accommodate the variations in delay differences due to environmental changes. Moreover, the modeling attack resistance of DDQ-APUF is evaluated, and a strategy for improving this resistance by incorporating pseudo-XOR technique is proposed. The circuit was implemented on Xilinx Artix-7 FPGAs and the experimental results show that the reliability achieves 99.95% with non-CRP-discard.
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作为一种轻量级硬件安全基元,物理不可克隆函数(PUF)可以为资源有限的物联网(IoT)设备提供可靠的身份验证。仲裁器 PUF(APUF)是最著名的 PUF 电路之一。然而,其硬件实现在现场可编程门阵列(FPGA)上的可靠性较差。本文提出了一种采用延迟差量化策略(DDQ-APUF)的高可靠性 APUF。通过在传统 APUF 的两条对称路径上添加多个可配置的延迟单元,收集 APUF 在不同延迟配置下的输出,即可获得 APUF 两条对称路径之间的延迟差。与传统 APUF 相比,DDQ-APUF 不以两条对称路径的信号传输仲裁结果作为响应,而是以两条路径的量化延迟差作为响应。认证中采用了容差阈值,以适应环境变化引起的延迟差变化。此外,还评估了 DDQ-APUF 的建模抗攻击性,并提出了通过采用伪 XOR 技术提高抗攻击性的策略。电路在 Xilinx Artix-7 FPGA 上实现,实验结果表明,在不丢弃 CRP 的情况下,可靠性达到了 99.95%。
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来源期刊
IEEE Transactions on Circuits and Systems I: Regular Papers
IEEE Transactions on Circuits and Systems I: Regular Papers 工程技术-工程:电子与电气
CiteScore
9.80
自引率
11.80%
发文量
441
审稿时长
2 months
期刊介绍: TCAS I publishes regular papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: - Circuits: Analog, Digital and Mixed Signal Circuits and Systems - Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic - Circuits and Systems, Power Electronics and Systems - Software for Analog-and-Logic Circuits and Systems - Control aspects of Circuits and Systems.
期刊最新文献
Table of Contents IEEE Circuits and Systems Society Information IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information Guest Editorial Special Issue on Emerging Hardware Security and Trust Technologies—AsianHOST 2023
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