Novel Enhancement-Mode p-Channel GaN MOSFETs With an AlN Insert Layer

IF 4.1 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Electron Device Letters Pub Date : 2024-12-23 DOI:10.1109/LED.2024.3521276
Hai Huang;Maolin Pan;Qiang Wang;Xinling Xie;Yannan Yang;Xin Hu;Luyu Wang;Penghao Zhang;Min Xu;David Wei Zhang
{"title":"Novel Enhancement-Mode p-Channel GaN MOSFETs With an AlN Insert Layer","authors":"Hai Huang;Maolin Pan;Qiang Wang;Xinling Xie;Yannan Yang;Xin Hu;Luyu Wang;Penghao Zhang;Min Xu;David Wei Zhang","doi":"10.1109/LED.2024.3521276","DOIUrl":null,"url":null,"abstract":"In this work, an enhancement-mode (E-mode) p-channel GaN metal-oxide-semiconductor field-effect transistor (p-MOSFET) with a maximum ON-state current (<inline-formula> <tex-math>${I}_{\\text {ON}}$ </tex-math></inline-formula>) density of 10.5 mA/mm, threshold voltage (<inline-formula> <tex-math>${V}_{\\text {TH}}$ </tex-math></inline-formula>) of −2.45 V, and <inline-formula> <tex-math>${I}_{\\text {ON}}/{I}_{\\text {OFF}}$ </tex-math></inline-formula> ratio of <inline-formula> <tex-math>$10^{{8}}$ </tex-math></inline-formula> is demonstrated on a commercial GaN wafer designed on a p-GaN HEMT. Furthermore, we present a novel E-mode p-FET featuring an AlN insertion layer within the p-GaN layer. The AlN layer introduces extra capacitance in the conducting channel and decreases the body factor m of devices. The p-GaN/AlN/p-GaN/AlGaN structure reduces the equivalent channel capacitance, achieving a minimum point-by-point subthreshold swing (SS) of 60 mV/dec. Compared with that of the conventional p-GaN channel FET, the SS decreases from 225 to 105 mV/dec over three orders, the <inline-formula> <tex-math>${V}_{\\text {TH}}$ </tex-math></inline-formula> shifts to −3.05 V, the <inline-formula> <tex-math>${I}_{\\text {ON}}/{I}_{\\text {OFF}}$ </tex-math></inline-formula> ratio increases to <inline-formula> <tex-math>$2 \\times 10^{{8}}$ </tex-math></inline-formula>, and the device also has an ultralow off-state leakage current in the range of <inline-formula> <tex-math>$10 \\; ^{-{8}}$ </tex-math></inline-formula> mA/mm. The proposed structure is compelling for GaN-based complementary metal-oxide-semiconductor (CMOS) logic and power devices.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 2","pages":"159-162"},"PeriodicalIF":4.1000,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10812025/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
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Abstract

In this work, an enhancement-mode (E-mode) p-channel GaN metal-oxide-semiconductor field-effect transistor (p-MOSFET) with a maximum ON-state current ( ${I}_{\text {ON}}$ ) density of 10.5 mA/mm, threshold voltage ( ${V}_{\text {TH}}$ ) of −2.45 V, and ${I}_{\text {ON}}/{I}_{\text {OFF}}$ ratio of $10^{{8}}$ is demonstrated on a commercial GaN wafer designed on a p-GaN HEMT. Furthermore, we present a novel E-mode p-FET featuring an AlN insertion layer within the p-GaN layer. The AlN layer introduces extra capacitance in the conducting channel and decreases the body factor m of devices. The p-GaN/AlN/p-GaN/AlGaN structure reduces the equivalent channel capacitance, achieving a minimum point-by-point subthreshold swing (SS) of 60 mV/dec. Compared with that of the conventional p-GaN channel FET, the SS decreases from 225 to 105 mV/dec over three orders, the ${V}_{\text {TH}}$ shifts to −3.05 V, the ${I}_{\text {ON}}/{I}_{\text {OFF}}$ ratio increases to $2 \times 10^{{8}}$ , and the device also has an ultralow off-state leakage current in the range of $10 \; ^{-{8}}$ mA/mm. The proposed structure is compelling for GaN-based complementary metal-oxide-semiconductor (CMOS) logic and power devices.
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来源期刊
IEEE Electron Device Letters
IEEE Electron Device Letters 工程技术-工程:电子与电气
CiteScore
8.20
自引率
10.20%
发文量
551
审稿时长
1.4 months
期刊介绍: IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.
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