Unveiling the Impact of Interfacial Trap Charges on Strained VS-FeFinFETs for Improved Reliability:Device to Circuit Level Assessment

Abstract

This paper focuses on the device to circuit level assessment of Si/SiGe strained vertically stacked ferroelectric based FinFETs (VS-FeFinFETs) for improved reliability under the influence of interfacial trap charges (ITCs) at the semiconductor/oxide interface. The device is designed with the amalgamation of several advanced technologies such as SOI, strained tri-layered silicon channel system along with the integration of ferroelectric material in superior gate controlled FinFET. Gate engineering has also been incorporated to further improve the device's reliability against ITCs, forming hetero dielectric vertically stacked ferroelectric based FinFET (HD-VS-FeFinFET) and it is found to possess superior analog, linearity, and harmonic distortion performance. It shows 91.48% reduction in leakage current resulting in 13 times increment in switching ratio along with improvement in quality factor by 46.01%, transconductance by 32.77%, and device efficiency by 26.54% with negligible variations due to ITCs as compared to VS-FeFinFET. Various linearity and harmonic parameters also improved and showed negligible average variations like 4.72% (177.15% ) in VIP2 and 6.525% (25.3% ) in 1-dB compression point for HD-VS-FeFinFET (VS-FeFinFET) against different ITCs polarity making it more reliable for low power microwave and distortion less wireless communication applications. Further logic circuit application of HD-VS-FeFinFET based CMOS inverter has been analysed and it shows improvement by 17.9% in transition range, 51.674% in voltage gain along with ITCs induced average variation of 3.66% (15.88% ) in noise margin for HD-VS-FeFinFET(VS-FeFinFET) based circuit thus led to its development with enhanced functionality, reliability, and performance, poised to shape the landscape of modern electronics.