Lower bound proof for the size of BDDs representing a shifted addition

Abstract

Decision Diagrams (DDs) are among the most popular representations for Boolean functions. They are widely used in the synthesis and verification of digital circuits. The size (i.e., number of nodes) and computation time (required time for performing operations) are two important parameters that determine the efficiency of a DD in different applications. It has been proven that some DDs can represent specific functions in polynomial space or perform certain operations in polynomial time. For example, Binary Decision Diagrams (BDDs) are capable of representing a wide variety of functions (e.g. integer addition) in polynomial space with respect to the input size. However, there are also some functions (e.g., integer multiplication) for which the exponential lower-bounds have been proven for the BDD sizes.

In this paper, we investigate the space complexity of representing an integer addition, where one of the operands is shifted to the right by an arbitrary value. We call this function the shifted addition. This function is widely used in many digital circuits, e.g., floating point adders. We prove that the size of the BDD representing a shifted addition has exponential space complexity with respect to the input size. It is an important step towards clarifying the reasons behind the failure of BDD-based verification and synthesis when they are applied to the circuits containing shifted addition, e.g., floating point adders.