Zhizhi Chen, Qian Wang, Houpeng Chen, Xi Li, Xiaogang Chen, Sannian Song, Zhitang Song
{"title":"Research and Improvement of Muller C Element","authors":"Zhizhi Chen, Qian Wang, Houpeng Chen, Xi Li, Xiaogang Chen, Sannian Song, Zhitang Song","doi":"10.1049/ell2.70184","DOIUrl":null,"url":null,"abstract":"<p>The basic structure of conventional Muller C element is studied and the output errors caused by node parasitic capacitors are analysed in this letter. In order to avoid such errors, an improved C element with two inverted ratio MOS transistors added is proposed to control high resistance nodes of the circuit. To reduce the power consumption of C element, two resistors are added. The proposed C element has been designed in 28 nm CMOS process and 2.5 V devices are adopted. The simulation results show that proposed C element avoids such errors and the size of the layout is 67.33 µm<sup>2</sup>.</p>","PeriodicalId":11556,"journal":{"name":"Electronics Letters","volume":"61 1","pages":""},"PeriodicalIF":0.8000,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/ell2.70184","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electronics Letters","FirstCategoryId":"5","ListUrlMain":"https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/ell2.70184","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
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Abstract
The basic structure of conventional Muller C element is studied and the output errors caused by node parasitic capacitors are analysed in this letter. In order to avoid such errors, an improved C element with two inverted ratio MOS transistors added is proposed to control high resistance nodes of the circuit. To reduce the power consumption of C element, two resistors are added. The proposed C element has been designed in 28 nm CMOS process and 2.5 V devices are adopted. The simulation results show that proposed C element avoids such errors and the size of the layout is 67.33 µm2.
期刊介绍：
Electronics Letters is an internationally renowned peer-reviewed rapid-communication journal that publishes short original research papers every two weeks. Its broad and interdisciplinary scope covers the latest developments in all electronic engineering related fields including communication, biomedical, optical and device technologies. Electronics Letters also provides further insight into some of the latest developments through special features and interviews.
Scope
As a journal at the forefront of its field, Electronics Letters publishes papers covering all themes of electronic and electrical engineering. The major themes of the journal are listed below.
Antennas and Propagation
Biomedical and Bioinspired Technologies, Signal Processing and Applications
Control Engineering
Electromagnetism: Theory, Materials and Devices
Electronic Circuits and Systems
Image, Video and Vision Processing and Applications
Information, Computing and Communications
Instrumentation and Measurement
Microwave Technology
Optical Communications
Photonics and Opto-Electronics
Power Electronics, Energy and Sustainability
Radar, Sonar and Navigation
Semiconductor Technology
Signal Processing
MIMO
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