Evaluation of random process fluctuation and geometry dependence in nanosheet reconfigurable transistor

Abstract

This study presents the first comprehensive evaluation of the impact of random process fluctuations on the electrical characteristics of nanosheet Reconfigurable FETs (NS-RFETs), and the geometry dependence including nanosheet width ($W_{NS}$) and thickness ($T_{NS}$) are also investigated. Utilizing MATLAB and 3-D TCAD simulations, this research addresses three key fluctuation sources such as work function variation (WFV), gate edge roughness (GER) and line edge roughness (LER) including line width roughness (LWR) and line height roughness (LHR). It reveals that the variation of $I_{ON}$ is the most influenced among all Figures of Merit (FoMs) and is predominantly affected by LWR and WFV at the control gate, due to the unique Schottky barrier tunneling mechanism in RFETs. WFV is the decisive factor for the variation of $V_{TH}$ and SS. Generally, smaller geometry parameter leads to deterioration in the variation of $V_{TH}$ and $SS$, and $I_{ON}$ is influenced more significantly. During the shrinkage of $W_{NS}$, the impact of LWR becomes more dominant on $I_{ON}$ and when $T_{NS}$ decreases, WFV becomes more dominant. And LWR and WFV still deserves special attention as the geometry scales down. The results also indicate that enhancing the uniformity of metal grain of metal gate and reducing the RMS of LWR and LHR can mitigate electric performance fluctuations.