JiaXin Tang , YaLian Wu , ChunYuan Ou , Pengcheng Zhong , Xue Zhao , Minglin Ma
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引用次数: 0
Abstract
The functional network of the human brain exhibits scale-free topology, and there are inevitable time delays in information transmission between neurons. This study explores the relationship between synchronization transitions and heterogeneous time delays in scale-free neuronal networks, as well as the influence of coupling strength on the synchronization process under the premise of introducing heterogeneous time delays. Inspired by small-world network construction methods, we designed a scale-free neural network model with heterogeneous time delays based on the Rulkov neuron model, referred to as the Heterogeneous Scale-Free Neural Network (HSFNN). In this paper, we propose a time delay determination mechanism (TDDM). Subsequently, we conducted numerical simulations to analyze the effects of various parameters related to time delays on the synchronization of HSFNNs. The results were analyzed using spatiotemporal state diagrams, recursion diagrams, and node state diagrams. The findings indicate that HSFNNs exhibit various dynamical phenomena, such as asynchronous, synchronous, and alternating states of synchronization and asynchrony. Furthermore, we found that altering coupling strength under the premise of introducing heterogeneous time delays also affects the synchronization states of HSFNNs.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.