Comprehensive Study of the Impact of LWR on Device Performance in VLSI Technology

Abstract

Line Width Roughness (LWR) has emerged as a pivotal challenge that the semiconductor manufacturing industry must confront. This study provides experimental data to elucidate the mechanism by which LWR affects device performance in different processing layers. First, Hard Mask (HM) technology was used to reduce LWR of Active Area (AA) and polysilicon gate by 0.97 nm and 0.62 nm, respectively, resulting in a 21.79% and 55.82% decrease in threshold voltage variability. With the application of HM technology in AA layer processing, the device performance of NMOS and PMOS was also improved by 19.58% and 12.54%, respectively. This improvement can be attributed to the mitigation of carrier scattering induced by LWR. Moreover, HM technology was also conducted in polysilicon gate process which can reduce LWR effectively, thereby enhancing device stability, decreasing the drain-induced barrier lowering factor by approximately 10%, and suppressing gate-induced drain leakage current and overlap capacitance. Consequently, this process contributes to the alleviation of short channel effects. Our research provides experimental groundwork for diminishing LWR, supplies guidelines for understanding the distinct mechanisms of LWR, and offers effective route toward enhancing device performance, and controlling fluctuations.