An Area/Power-Efficient Noise-Shaping SAR ADC for Implantable Biosensor Applications Featuring a Unique Auxiliary Feedback Loop

IF 3.1 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-10-23 DOI:10.1109/TVLSI.2024.3477717
Weihao Wang;Kong-Pang Pun
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Abstract

Wide bandwidth and power-area efficient front-ends are required in emerging implantable biosensor applications, e.g., wireless artificial vision systems for the limited vision. This work presents a low-power 0.031 mm $^{2}~3$ -MHz bandwidth noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) tailored for implantable biosensor applications. A highly energy- and area-efficient reset-free residue-processing scheme is proposed. This scheme facilitates noise transfer function (NTF) optimization by enabling control over complex poles. It establishes a unique auxiliary feedback path from the infinite impulse response (IIR) back to the finite impulse response (FIR) by eliminating the need for the FIR filter’s reset phase. This auxiliary feedback loop, which could not be achieved in previous FIR-IIR structures, is a key enabler for achieving high energy efficiency and design flexibility. The in-band quantization noise suppression is boosted by the proposed complex conjugate poles optimization technique, while a low $kT/C$ input-referred noise has resulted. The prototype, fabricated in 65-nm CMOS technology with a 7-bit digital-to-analog converter (DAC), consumes $370~\mu $ W from a 1-V supply and occupies an active area of only $0.17\times 0.18$ mm (0.031-mm2). Operating at an 80-MHz oversampling frequency, the proposed ADC achieves a signal-to-noise and distortion ratio (SNDR) of 70.2 dB over a 3 MHz bandwidth, demonstrating its small area, high efficiency, and high performance for implantable biosensor applications that require high data rates.
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具有独特辅助反馈回路的可植入生物传感器应用的面积/功率高效噪声整形SAR ADC
在新兴的植入式生物传感器应用中,例如用于视力受限的无线人工视觉系统,需要宽带和功率区域高效的前端。本研究提出了一种低功耗0.031 mm $^{2}~3$ -MHz带宽噪声整形(NS)逐次逼近寄存器(SAR)模数转换器(ADC),专为植入式生物传感器应用而设计。提出了一种高能量和面积效率的无复位剩余物处理方案。该方案通过实现对复杂极点的控制,促进了噪声传递函数(NTF)的优化。它通过消除FIR滤波器的复位相位,建立了从无限脉冲响应(IIR)到有限脉冲响应(FIR)的唯一辅助反馈路径。这种辅助反馈回路是以前的FIR-IIR结构无法实现的,是实现高能效和设计灵活性的关键因素。本文提出的复共轭极点优化技术提高了带内量化噪声抑制能力,同时产生了较低的输入参考噪声。该原型采用65纳米CMOS技术和7位数模转换器(DAC)制造,从1 v电源消耗370~\mu $ W,占用的有效面积仅为0.17\ × 0.18$ mm (0.031 mm2)。该ADC工作在80 MHz的过采样频率下,在3 MHz的带宽上实现了70.2 dB的信噪比和失真比(SNDR),证明了其小面积、高效率和高性能,适用于需要高数据速率的植入式生物传感器应用。
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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