Investigation of stability parameters of a gate-stack junctionless double-gate transistor (GS-JLDGT)-based 6T and 3T SRAM in the presence of traps

Abstract

In light of the continuously rising demand for portable handheld devices in day-to-day life and in specific applications such as biomedical systems (blood pressure monitors, pacemakers, and hearing aids), stable digital systems with low area and power consumption are required. Static random-access memory (SRAM) is a fundamental component of digital systems, and hence stable and efficient design of SRAM is critical. This paper reports on the stability and reliability of a SRAM device designed using a gate-stack junctionless double-gate transistor (GS-JLDGT). The proposed GS-JLDGT is used to implement a six-transistor (6T) SRAM, and the GS-JLDGT structure is then modified by adding an oxide layer in the middle and utilized to design a 3T SRAM. As a result, the area occupied by the proposed 3T SRAM is reduced by almost half as compared to a conventional 6T SRAM layout. The reliability assessment of the designed SRAM is carried out by the inclusion of interface trap charges at the oxide–semiconductor interface. The results show that the presence of the interface trap charges leads to degradation in the voltage transfer curve (VTC) and hence significant deviations in various stability parameters, including the retention noise margin (RNM), static noise margin (SNM), static voltage noise margin (SVNM), static current noise margin (SINM), write trip voltage (WTV), and write trip current (WTI) of the device. In addition, the impact of temperature variation along with trap charges is investigated with respect to the stability of the GS-JLDGT-based 6T SRAM. The results indicate that as the temperature increases, distortion due to trap charges also increases significantly.