An Adaptive Maintain Power Signature (MPS) Scheme With Reusable Current Generator for Powered Device (PD)

IF 3.1 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-10-28 DOI:10.1109/TVLSI.2024.3480955

Yongyuan Li;Xuhong Yin;Wei Guo;Qiang Wu;Yongbo Zhang;Yong You;Zhangming Zhu

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Abstract

The power over Ethernet (PoE) technology has gained intensive attention in networking market owing to the advantages of compactness, flexibility, and cost in application. The automatic maintain power signature (MPS) function specified by IEEE standard extracts the periodic pulsed current to enable applications requiring low power modes. However, a large driving capacity is required due to a large MPS current above 10 mA, sacrificing a certain area. This brief proposes an adaptive MPS scheme, which reuses existing class regulator and delay timer to source a pulsed MPS current to meet the MPS requirements, saving an area of 0.0104 mm2. The proposed MPS scheme has been fabricated in 0.18-

$\mu $

m 120-V BCD process and the area is

$1.37\times 1.00$

mm2. The experimental results show that the proposed PoE interface draws a pulsed current with a period of 312 ms and 25.6% duty cycle to address the issue of MPS absence in very low-power standby modes.

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基于可复用电流发生器的自适应维持功率签名（MPS）方案

PoE （power over Ethernet，以太网供电）技术以其结构紧凑、灵活、应用成本低等优点受到网络市场的广泛关注。IEEE标准规定的自动保持功率特征（MPS）功能提取周期性脉冲电流，以支持需要低功耗模式的应用。然而，由于10 mA以上的大MPS电流，需要大的驱动容量，牺牲一定的面积。本文提出了一种自适应MPS方案，该方案重用现有的类稳压器和延迟定时器来产生脉冲MPS电流以满足MPS要求，节省了0.0104 mm2的面积。所提出的MPS方案已在0.18- $ $ μ $ m 120 v BCD工艺中制备，面积为$1.37\ × 1.00$ mm2。实验结果表明，所提出的PoE接口产生的脉冲电流周期为312 ms，占空比为25.6%，可以解决极低功耗待机模式下MPS缺失的问题。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.