Physical Compact Model for Source-Gated Transistors for DC Application

Abstract

We present the first physical compact model for an amorphous silicon source-gated transistor (SGT) with variable Schottky barrier height. The previously published empirical compact model and TCAD model of an SGT are used to identify dominant effects present. The compact model is then validated on real device measurements. The compact model aims to operate under common conditions and typically desirable regimes of operation for an SGT, such as the flat saturation regime occurring at a particularly low saturation voltage. The dominant injection mechanisms occur through thermionic and thermionic field emission, which are the contact effects present in an SGT. Thermionic emission tends to be dominant under most common conditions. The model is suitably accurate to be used as a representation of an SGT in a SPICE simulation. This can be seen as a first step toward analog circuit design with SGTs as compact models enable circuit designers to utilize new and unique devices.