Design for an 81% Peak PDP and 0.33-cps/μm² DCR Si-SPADs at 5-V Excess Bias Voltage Based on 180-nm BCD Technology

Abstract

A high-performance single-photon avalanche diode (SPAD) is proposed based on 180-nm bipolar-CMOS-DMOS (BCD) technology. To enhance the photon detection probability (PDP), the primary multiplication region is formed at the interface of the P-type enrichment and high-voltage N-well (HVNW), which is deeper than that in traditional SPADs. At the same time, two extended multiplication regions on either side of the HVNW further facilitate the detection of photons. Lightly doped p-type epitaxial (P-epi) layers associated with the shallow trench isolation (STI) are introduced as guard rings to prevent premature edge breakdown (PEB) and reduce dark count rate (DCR). In particular, we investigate the impacts of various device parameters, including the guard ring width (GRW), the distance between STI and P-type enrichment, and the distance of P+ extending from the P-type enrichment on the performance of the SPADs. Through parametric optimization, the proposed SPAD obtains a high peak PDP of 81% at 555 nm and a near-infrared (NIR) PDP of 7.54% at 905 nm with a low DCR of 0.33 cps/ $\mu $ m2 at an excess voltage ( ${V} _{\text {ex}}$ ) of 5 V. The full-width at half-maximum (FWHM) of the timing jitter at 905-nm wavelength is 220 ps. The optimized SPADs can be integrated into high-density arrays for low-cost imaging sensor applications.