Understanding of the Electrostatic Coupling in Flip FET (FFET) and Corresponding Strategies

Abstract

Flip FET (FFET), a novel self-aligned stacked transistor architecture with dual-sided transistor stacking, was recently proposed and demonstrated. However, due to the vertically stacking nature, the electrical coupling of frontside (FS) and backside (BS) transistors should be carefully examined. Here, we thoroughly investigated the coupling effects of FFET at both device and circuit levels using TCAD simulation. For the device level assessment, the coupling effects are measured by the threshold voltage ( ${V}_{\text {th}}$ ) shift and the subthreshold swing (SS) degradation of transistors, as a result of the bias applied on the other side’s transistors. At the circuit level, the propagation delay of FFET inverters was studied. In the worst case scenario, the ${V}_{\text {th}}$ shift is up to 135 mV, the SS degradation up to 235 mV/dec (from 72.6 mV/dec), and the inverter’s delay change up to 4.41% is found, which is undesired and intolerable for circuit designs. To address this issue, a novel middle dielectric isolation (MDI) technique was proposed and found to be quite effective in blocking the electrical field from the other side, thus reducing the coupling effects. By implementing the MDI technique, the ${V}_{\text {th}}$ shift of no more than 0.85 mV, negligible SS degradation, and the INV’s delay change of less than 0.6% are realized. We also investigated MDI FFET’s gate structure innovations [e.g., Pi-gate, omega-gate (OG), and gate-all-around (GAA)] to enhance the gate control, by which the ${V} _{\text {th}}$ shift can be minimized to 0.12 mV. This work paves the way for practical implementation of FFET in the future.