Lightweight FPGA acceleration framework for structurally tailored multi-version MobileNetV1

Abstract

Convolutional neural networks (CNNs) have significantly enhanced image recognition performance through effective feature extraction and weight sharing, establishing themselves as a pivotal research area in computer vision. Despite these advances, CNNs demand substantial computational resources, posing challenges for deployment on resource-constrained embedded devices. Consequently, lightweight CNN models, such as MobileNet, have been developed to optimize computational efficiency. However, these models still necessitate accelerators to achieve optimal performance. Field-programmable gate arrays (FPGAs) present a viable solution for accelerating lightweight CNN models, thanks to their inherent capabilities for high parallelism, superior energy efficiency compared to traditional CPUs or GPUs, and reconfigurability, which adapts well to evolving network architectures. Nevertheless, compact FPGAs are limited by their on-chip logic resources. This limitation, coupled with the requirement to support multiple pruned versions of MobileNet networks due to advancements in model structure pruning, complicates the FPGA design process and escalates the resource allocation and associated costs. To address this issue, we propose a master-slave architecture for the MobileNetV1 computing framework, where the master module manages task scheduling and resource allocation, while slave modules execute the actual convolutional computations. This framework employs a dynamic configuration method, programming execution parameters for each network layer into the FPGA, allowing adaptability and optimization of resource usage. The proposed design was validated on the Altera De2-115 FPGA evaluation board using the MobileNet-V1-0.5-160 model. Experimental results demonstrated that, when implemented on the Altera De2-115 FPGA board, the recognition speed of our optimized MobileNetV1 model could reach 68.9 frames per second (FPS) with an 8-bit data width and a clock speed of 25 MHz, utilizing only 38K logic units—an efficient performance benchmark compared to previous FPGA implementations.