A 225-GHz Coupled Harmonic Oscillator With −179 dBc/Hz FoM in 65-nm CMOS

Abstract

This letter presents a 225-GHz coupled second harmonic oscillator. The single-ended oscillator core utilizes a piecewise linear model with a phase factor to analyze the impact of the large-signal fundamental ($\bm {f}_{\bm {0}}$) voltages on the second-harmonic ($\bm {2f}_{\bm {0}}$) current, enabling the selection of optimal transistor conditions for efficient $\bm {f}_{\bm {0}}$ oscillation and $\bm {2f}_{\bm {0}}$ generation. To achieve good phase noise and output power performance, the coupling scheme of eight oscillator cores is proposed without extra components to suppress unwanted modes. Fabricated in a 65-nm CMOS process, the coupled oscillator generates 0.407-mW output power while consuming 40.5 mW from a 0.75-V power supply voltage. The measured dc-to-RF efficiency of the oscillator is 1% and the phase noise is −88 dBc/Hz at 1 MHz offset, resulting in a figure of merit of −179 dBc/Hz.