Fabrication of Highly Ordered Macropore Arrays in p-Type Silicon by Electrochemical Etching: Effect of Wafer Resistivity and Other Etching Parameters.

Abstract

Macroporous silicon is a promising substrate in the field of optics, electronics, etc. In this paper, highly ordered macropore arrays were fabricated in p-type silicon wafers by electrochemical etching using a double-tank cell. The effect of the silicon resistivity, etching voltage and etching time on the pore morphology was investigated and the influence mechanism was analyzed. The pore diameter would decrease with the increase in the silicon resistivity and the decrease in the etching voltage, due to the increase in the space charge region width (SCRL). The pore depth would increase with the resistivity and the voltage. However, too high resistivity would cause insufficiency at the pore tips and too high voltage would cause pore splitting, which may cause a decrease in the pore depth. Then, the aspect ratio of 21 can be obtained on the silicon wafer with a resistivity of 50-80 Ω·cm at the etching voltage of 5 V with a maximum etching rate of about 0.92 μm/min.