{"title":"Design of a low-power, low-PDP dual modulus CML frequency divider for ZigBee application","authors":"Lokenath Kundu , Subhanil Maity , Sourav Nath , Gaurav Singh Baghel , Krishna Lal Baishnab","doi":"10.1016/j.vlsi.2025.102400","DOIUrl":null,"url":null,"abstract":"<div><div>This work presents novel single-ended (Design I and Design II) and double-ended (Design III and Design IV) architectures of 2/3 frequency dividers (FDs) that improve power delay product (PDP) and power consumption. This novel work proposes four kinds of 2/3 dual modulus FDs that are compatible with ZigBee and Bluetooth communication standards. The proposed designs are also tunable for different communication bands and are based on current mode logic (CML) in the 2.4–2.8 GHz PLL application range. The subblocks of 2/3 dual modulus FDs use CML-based latches, XOR gates, and delay cells to achieve the desired functionality. The g<sub>m</sub> over I<sub>d</sub> (g<sub>m</sub>/I<sub>d</sub>) methodology is explored for the optimum design of latches, enabling efficient circuit sizing and enhanced performance. This lowers the total power consumption to 0.6 mW with a power delay product (PDP) of 1 fJ. These proposed designs are post-layout simulated using a TSMC 65 nm CMOS process technology node. These designs are compared with the recent post-layout performances of state-of-the-art works with 30.6 dB of figure of merits (FoM). This work entails statistical analysis (Monte Carlo (MC)) as well as variations in process, supply voltage, and temperature (PVT analysis) in accordance with the AEC-Q100 standard (Grade 1).</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102400"},"PeriodicalIF":2.2000,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926025000574","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
This work presents novel single-ended (Design I and Design II) and double-ended (Design III and Design IV) architectures of 2/3 frequency dividers (FDs) that improve power delay product (PDP) and power consumption. This novel work proposes four kinds of 2/3 dual modulus FDs that are compatible with ZigBee and Bluetooth communication standards. The proposed designs are also tunable for different communication bands and are based on current mode logic (CML) in the 2.4–2.8 GHz PLL application range. The subblocks of 2/3 dual modulus FDs use CML-based latches, XOR gates, and delay cells to achieve the desired functionality. The gm over Id (gm/Id) methodology is explored for the optimum design of latches, enabling efficient circuit sizing and enhanced performance. This lowers the total power consumption to 0.6 mW with a power delay product (PDP) of 1 fJ. These proposed designs are post-layout simulated using a TSMC 65 nm CMOS process technology node. These designs are compared with the recent post-layout performances of state-of-the-art works with 30.6 dB of figure of merits (FoM). This work entails statistical analysis (Monte Carlo (MC)) as well as variations in process, supply voltage, and temperature (PVT analysis) in accordance with the AEC-Q100 standard (Grade 1).
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.