Lintao Li , Xiaoxia Yao , Yimin Li , Ran Zhu , Jiayi Lv , Hua Li
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引用次数: 0
Abstract
This paper presents a resource-efficient, ultra-high throughput low density parity check (LDPC) decoder that is suitable for tens of gigabit bits per second satellite communications. To address routing congestion and critical path delay, which are typically caused by the high degree of parallelism in high throughput decoder designs, this work introduces an efficient computation circuit for identifying the two minimum values in the check node update process. Furthermore, a non-uniform quantization method based on mutual information maximization is proposed for log-likelihood ratio (LLR) representation, enabling a more favorable trade-off between decoding performance and implementation complexity. Additionally, the decoder utilizes a pipelined multi-frame parallel scheduling scheme, which significantly boosts throughput with only a slight increase in storage requirements. Finally, the proposed design is implemented and tested on a Xilinx UltraScale+ XCVU13P FPGA. The results show that the decoder achieves a throughput of 76.5Gbps at 8 iterations and 200MHz. This implementation outperforms existing designs, highlighting the innovative and superior nature of our approach.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.